tests/asicworld/code_tidbits_wire_example.v - third_party/yosys - Git at Google

 module wire_example( a, b, y);
   input a, b;
   output y;

   wire a, b, y;

   assign y = a & b;

 endmodule
	module wire_example( a, b, y);
	input a, b;
	output y;

	wire a, b, y;

	assign y = a & b;

	endmodule