Add new $__DFFS* cells
diff --git a/passes/hierarchy/clkpart.cc b/passes/hierarchy/clkpart.cc index 81983e2..2bc9f49 100644 --- a/passes/hierarchy/clkpart.cc +++ b/passes/hierarchy/clkpart.cc
@@ -166,7 +166,22 @@ ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_))) { bool this_clk_pol = cell->type.in(ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_)); - log_assert(!enable_mode); // TODO + log_assert(!enable_mode); // TODO: Consider async S/R signals + key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), true, RTLIL::SigSpec()); + } + else + if (cell->type.in(ID($__DFFS_NN0_), ID($__DFFS_NN1_), ID($_DFFS_NP0_), ID($_DFFS_NP1_), + ID($__DFFS_PN0_), ID($__DFFS_PN1_), ID($_DFFS_PP0_), ID($_DFFS_PP1_))) + { + bool this_clk_pol = cell->type.in(ID($_DFFS_PN0_), ID($_DFFS_PN1_), ID($_DFFS_PP0_), ID($_DFFS_PP1_)); + log_assert(!enable_mode); // TODO: Consider sync S/R signals + key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), true, RTLIL::SigSpec()); + } + if (cell->type.in(ID($__DFFSE_NN0_), ID($__DFFSE_NN1_), ID($_DFFSE_NP0_), ID($_DFFSE_NP1_), + ID($__DFFSE_PN0_), ID($__DFFSE_PN1_), ID($_DFFSE_PP0_), ID($_DFFSE_PP1_))) + { + bool this_clk_pol = cell->type.in(ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_)); + log_assert(!enable_mode); // TODO: Consider sync S/R and enable signals key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), true, RTLIL::SigSpec()); } else
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 211f961..396d76a 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc
@@ -266,6 +266,23 @@ ct.setup_stdcells_mem(); ct.setup_design(design); + ct.setup_type(ID($__DFFS_NN0_), {ID(D),ID(C),ID(R)}, {ID(Q)}); + ct.setup_type(ID($__DFFS_NN1_), {ID(D),ID(C),ID(R)}, {ID(Q)}); + ct.setup_type(ID($__DFFS_NP0_), {ID(D),ID(C),ID(R)}, {ID(Q)}); + ct.setup_type(ID($__DFFS_NP1_), {ID(D),ID(C),ID(R)}, {ID(Q)}); + ct.setup_type(ID($__DFFS_PN0_), {ID(D),ID(C),ID(R)}, {ID(Q)}); + ct.setup_type(ID($__DFFS_PN1_), {ID(D),ID(C),ID(R)}, {ID(Q)}); + ct.setup_type(ID($__DFFS_PP0_), {ID(D),ID(C),ID(R)}, {ID(Q)}); + ct.setup_type(ID($__DFFS_PP1_), {ID(D),ID(C),ID(R)}, {ID(Q)}); + ct.setup_type(ID($__DFFSE_NN0_), {ID(D),ID(C),ID(R),ID(E)}, {ID(Q)}); + ct.setup_type(ID($__DFFSE_NN1_), {ID(D),ID(C),ID(R),ID(E)}, {ID(Q)}); + ct.setup_type(ID($__DFFSE_NP0_), {ID(D),ID(C),ID(R),ID(E)}, {ID(Q)}); + ct.setup_type(ID($__DFFSE_NP1_), {ID(D),ID(C),ID(R),ID(E)}, {ID(Q)}); + ct.setup_type(ID($__DFFSE_PN0_), {ID(D),ID(C),ID(R),ID(E)}, {ID(Q)}); + ct.setup_type(ID($__DFFSE_PN1_), {ID(D),ID(C),ID(R),ID(E)}, {ID(Q)}); + ct.setup_type(ID($__DFFSE_PP0_), {ID(D),ID(C),ID(R),ID(E)}, {ID(Q)}); + ct.setup_type(ID($__DFFSE_PP1_), {ID(D),ID(C),ID(R),ID(E)}, {ID(Q)}); + for (auto port : module->ports) { auto wire = module->wire(port); if (wire->port_output)