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foss-fpga-tools
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third_party
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yosys
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a12fc783612f52aecdce6863e905dc245343a0ff
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.
/
tests
/
opt
/
opt_rmdff_sat.v
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module
top
(
input clk
,
output reg
[
7
:
0
]
cnt
);
initial cnt
=
0
;
always
@(
posedge clk
)
begin
if
(
cnt
<
20
)
cnt
<=
cnt
+
1
;
else
cnt
<=
0
;
end
endmodule