Google Git
Sign in
foss-fpga-tools/third_party/yosys/a5ac33f230b5dd20273f6636e5b573ef0478b8f9^1..a5ac33f230b5dd20273f6636e5b573ef0478b8f9/.
commit
a5ac33f230b5dd20273f6636e5b573ef0478b8f9
[log]
author
Eddie Hung <eddie@fpgeh.com>
Fri Oct 04 17:53:20 2019 -0700
committer
Eddie Hung <eddie@fpgeh.com>
Fri Oct 04 17:53:20 2019 -0700
tree
6f67a20084e1490fec10824cf4ff9eb4c6fe14e8
parent
aae2b9fd9c8dc915fadacc24962436dd7aedff36 [diff]
parent
0acc51c3d82f65f73fa9e475c6fc41beabd925a6 [diff]
Merge branch 'master' into eddie/abc_to_abc9

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index ded1cd6..bd2fd91 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc

@@ -3554,6 +3554,12 @@
 	if (width_ != other.width_)
 		return false;
 
+	// Without this, SigSpec() == SigSpec(State::S0, 0) will fail
+	//   since the RHS will contain one SigChunk of width 0 causing
+	//   the size check below to fail
+	if (width_ == 0)
+		return true;
+
 	pack();
 	other.pack();
 

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index c08653b..e5b24cc 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h

@@ -609,8 +609,11 @@
 	std::string decode_string() const;
 
 	inline int size() const { return bits.size(); }
+	inline bool empty() const { return bits.empty(); }
 	inline RTLIL::State &operator[](int index) { return bits.at(index); }
 	inline const RTLIL::State &operator[](int index) const { return bits.at(index); }
+	inline decltype(bits)::iterator begin() { return bits.begin(); }
+	inline decltype(bits)::iterator end() { return bits.end(); }
 
 	bool is_fully_zero() const;
 	bool is_fully_ones() const;

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 3d0b1f2..4e174e7 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg

@@ -277,7 +277,9 @@
 	index <SigBit> port(postAdd, AB)[0] === sigP[0]
 	filter GetSize(port(postAdd, AB)) >= GetSize(sigP)
 	filter port(postAdd, AB).extract(0, GetSize(sigP)) == sigP
-	filter port(postAdd, AB).extract_end(GetSize(sigP)) == SigSpec(sigP[GetSize(sigP)-1], GetSize(port(postAdd, AB))-GetSize(sigP))
+	// Check that remainder of AB is a sign-extension
+	define <bool> AB_SIGNED (param(postAdd, AB == \A ? \A_SIGNED : \B_SIGNED).as_bool())
+	filter port(postAdd, AB).extract_end(GetSize(sigP)) == SigSpec(AB_SIGNED ? sigP[GetSize(sigP)-1] : State::S0, GetSize(port(postAdd, AB))-GetSize(sigP))
 	set postAddAB AB
 	optional
 endmatch

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 1ebdaa2..27106cc 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc

@@ -247,7 +247,7 @@
 		bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str,
 		bool /*keepff*/, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,
 		bool show_tempdir, std::string box_file, std::string lut_file,
-		std::string wire_delay, const dict<int,IdString> &box_lookup
+		std::string wire_delay, const dict<int,IdString> &box_lookup, bool nomfs
 )
 {
 	module = current_module;
@@ -346,6 +346,10 @@
 	for (size_t pos = abc9_script.find("{W}"); pos != std::string::npos; pos = abc9_script.find("{W}", pos))
 		abc9_script = abc9_script.substr(0, pos) + wire_delay + abc9_script.substr(pos+3);
 
+	if (nomfs)
+		for (size_t pos = abc9_script.find("&mfs"); pos != std::string::npos; pos = abc9_script.find("&mfs", pos))
+			abc9_script = abc9_script.erase(pos, strlen("&mfs"));
+
 	abc9_script += stringf("; &write %s/output.aig", tempdir_name.c_str());
 	abc9_script = add_echos_to_abc9_cmd(abc9_script);
 
@@ -921,6 +925,7 @@
 		std::string delay_target, lutin_shared = "-S 1", wire_delay;
 		bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true;
 		bool show_tempdir = false;
+		bool nomfs = false;
 		vector<int> lut_costs;
 		markgroups = false;
 
@@ -1043,6 +1048,10 @@
 				wire_delay = "-W " + args[++argidx];
 				continue;
 			}
+			if (arg == "-nomfs") {
+				nomfs = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -1131,7 +1140,7 @@
 			if (!dff_mode || !clk_str.empty()) {
 				abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
 						delay_target, lutin_shared, fast_mode, show_tempdir,
-						box_file, lut_file, wire_delay, box_lookup);
+						box_file, lut_file, wire_delay, box_lookup, nomfs);
 				continue;
 			}
 
@@ -1277,7 +1286,7 @@
 				en_sig = assign_map(std::get<3>(it.first));
 				abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, !clk_sig.empty(), "$",
 						keepff, delay_target, lutin_shared, fast_mode, show_tempdir,
-						box_file, lut_file, wire_delay, box_lookup);
+						box_file, lut_file, wire_delay, box_lookup, nomfs);
 				assign_map.set(mod);
 			}
 		}

diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py
index 13dbc0e..ee20ae9 100644
--- a/techlibs/xilinx/cells_xtra.py
+++ b/techlibs/xilinx/cells_xtra.py

@@ -137,7 +137,7 @@
     Cell('SYSMON'),
 
     # Arithmetic functions.
-    Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}),
+    #Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}),
 
     # Clock components.
     # Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}),
@@ -264,7 +264,7 @@
     Cell('XADC'),
 
     # Arithmetic functions.
-    Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}),
+    #Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}),
 
     # Clock components.
     # Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}),

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 5c2b140..beefcd4 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc

@@ -475,13 +475,17 @@
 			else if (abc9) {
 				if (family != "xc7")
 					log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, "
-                            "will use timing for 'xc7' instead.\n", family.c_str());
+							"will use timing for 'xc7' instead.\n", family.c_str());
 				run("techmap -map +/xilinx/abc9_map.v -max_iter 1");
 				run("read_verilog -icells -lib +/xilinx/abc9_model.v");
+				std::string abc9_opts = " -box +/xilinx/abc9_xc7.box";
+				abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY);
+				abc9_opts += " -nomfs";
 				if (nowidelut)
-					run("abc9 -lut +/xilinx/abc9_xc7_nowide.lut -box +/xilinx/abc9_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
+					abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut";
 				else
-					run("abc9 -lut +/xilinx/abc9_xc7.lut -box +/xilinx/abc9_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
+					abc9_opts += " -lut +/xilinx/abc9_xc7.lut";
+				run("abc9" + abc9_opts);
 			}
 			else {
 				if (nowidelut)

diff --git a/techlibs/xilinx/xc6v_cells_xtra.v b/techlibs/xilinx/xc6v_cells_xtra.v
index b228e40..d9e06ea 100644
--- a/techlibs/xilinx/xc6v_cells_xtra.v
+++ b/techlibs/xilinx/xc6v_cells_xtra.v

@@ -647,94 +647,6 @@
     input [6:0] DADDR;
 endmodule
 
-module DSP48E1 (...);
-    parameter integer ACASCREG = 1;
-    parameter integer ADREG = 1;
-    parameter integer ALUMODEREG = 1;
-    parameter integer AREG = 1;
-    parameter AUTORESET_PATDET = "NO_RESET";
-    parameter A_INPUT = "DIRECT";
-    parameter integer BCASCREG = 1;
-    parameter integer BREG = 1;
-    parameter B_INPUT = "DIRECT";
-    parameter integer CARRYINREG = 1;
-    parameter integer CARRYINSELREG = 1;
-    parameter integer CREG = 1;
-    parameter integer DREG = 1;
-    parameter integer INMODEREG = 1;
-    parameter integer MREG = 1;
-    parameter integer OPMODEREG = 1;
-    parameter integer PREG = 1;
-    parameter SEL_MASK = "MASK";
-    parameter SEL_PATTERN = "PATTERN";
-    parameter USE_DPORT = "FALSE";
-    parameter USE_MULT = "MULTIPLY";
-    parameter USE_PATTERN_DETECT = "NO_PATDET";
-    parameter USE_SIMD = "ONE48";
-    parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
-    parameter [47:0] PATTERN = 48'h000000000000;
-    parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
-    parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
-    parameter [0:0] IS_CLK_INVERTED = 1'b0;
-    parameter [4:0] IS_INMODE_INVERTED = 5'b0;
-    parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
-    output [29:0] ACOUT;
-    output [17:0] BCOUT;
-    output CARRYCASCOUT;
-    output [3:0] CARRYOUT;
-    output MULTSIGNOUT;
-    output OVERFLOW;
-    output [47:0] P;
-    output PATTERNBDETECT;
-    output PATTERNDETECT;
-    output [47:0] PCOUT;
-    output UNDERFLOW;
-    input [29:0] A;
-    input [29:0] ACIN;
-    (* invertible_pin = "IS_ALUMODE_INVERTED" *)
-    input [3:0] ALUMODE;
-    input [17:0] B;
-    input [17:0] BCIN;
-    input [47:0] C;
-    input CARRYCASCIN;
-    (* invertible_pin = "IS_CARRYIN_INVERTED" *)
-    input CARRYIN;
-    input [2:0] CARRYINSEL;
-    input CEA1;
-    input CEA2;
-    input CEAD;
-    input CEALUMODE;
-    input CEB1;
-    input CEB2;
-    input CEC;
-    input CECARRYIN;
-    input CECTRL;
-    input CED;
-    input CEINMODE;
-    input CEM;
-    input CEP;
-    (* clkbuf_sink *)
-    (* invertible_pin = "IS_CLK_INVERTED" *)
-    input CLK;
-    input [24:0] D;
-    (* invertible_pin = "IS_INMODE_INVERTED" *)
-    input [4:0] INMODE;
-    input MULTSIGNIN;
-    (* invertible_pin = "IS_OPMODE_INVERTED" *)
-    input [6:0] OPMODE;
-    input [47:0] PCIN;
-    input RSTA;
-    input RSTALLCARRYIN;
-    input RSTALUMODE;
-    input RSTB;
-    input RSTC;
-    input RSTCTRL;
-    input RSTD;
-    input RSTINMODE;
-    input RSTM;
-    input RSTP;
-endmodule
-
 module BUFGCE (...);
     parameter CE_TYPE = "SYNC";
     parameter [0:0] IS_CE_INVERTED = 1'b0;

diff --git a/techlibs/xilinx/xc7_cells_xtra.v b/techlibs/xilinx/xc7_cells_xtra.v
index 0d16f81..f36e4ba 100644
--- a/techlibs/xilinx/xc7_cells_xtra.v
+++ b/techlibs/xilinx/xc7_cells_xtra.v

@@ -3376,94 +3376,6 @@
     input [6:0] DADDR;
 endmodule
 
-module DSP48E1 (...);
-    parameter integer ACASCREG = 1;
-    parameter integer ADREG = 1;
-    parameter integer ALUMODEREG = 1;
-    parameter integer AREG = 1;
-    parameter AUTORESET_PATDET = "NO_RESET";
-    parameter A_INPUT = "DIRECT";
-    parameter integer BCASCREG = 1;
-    parameter integer BREG = 1;
-    parameter B_INPUT = "DIRECT";
-    parameter integer CARRYINREG = 1;
-    parameter integer CARRYINSELREG = 1;
-    parameter integer CREG = 1;
-    parameter integer DREG = 1;
-    parameter integer INMODEREG = 1;
-    parameter integer MREG = 1;
-    parameter integer OPMODEREG = 1;
-    parameter integer PREG = 1;
-    parameter SEL_MASK = "MASK";
-    parameter SEL_PATTERN = "PATTERN";
-    parameter USE_DPORT = "FALSE";
-    parameter USE_MULT = "MULTIPLY";
-    parameter USE_PATTERN_DETECT = "NO_PATDET";
-    parameter USE_SIMD = "ONE48";
-    parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
-    parameter [47:0] PATTERN = 48'h000000000000;
-    parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
-    parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
-    parameter [0:0] IS_CLK_INVERTED = 1'b0;
-    parameter [4:0] IS_INMODE_INVERTED = 5'b0;
-    parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
-    output [29:0] ACOUT;
-    output [17:0] BCOUT;
-    output CARRYCASCOUT;
-    output [3:0] CARRYOUT;
-    output MULTSIGNOUT;
-    output OVERFLOW;
-    output [47:0] P;
-    output PATTERNBDETECT;
-    output PATTERNDETECT;
-    output [47:0] PCOUT;
-    output UNDERFLOW;
-    input [29:0] A;
-    input [29:0] ACIN;
-    (* invertible_pin = "IS_ALUMODE_INVERTED" *)
-    input [3:0] ALUMODE;
-    input [17:0] B;
-    input [17:0] BCIN;
-    input [47:0] C;
-    input CARRYCASCIN;
-    (* invertible_pin = "IS_CARRYIN_INVERTED" *)
-    input CARRYIN;
-    input [2:0] CARRYINSEL;
-    input CEA1;
-    input CEA2;
-    input CEAD;
-    input CEALUMODE;
-    input CEB1;
-    input CEB2;
-    input CEC;
-    input CECARRYIN;
-    input CECTRL;
-    input CED;
-    input CEINMODE;
-    input CEM;
-    input CEP;
-    (* clkbuf_sink *)
-    (* invertible_pin = "IS_CLK_INVERTED" *)
-    input CLK;
-    input [24:0] D;
-    (* invertible_pin = "IS_INMODE_INVERTED" *)
-    input [4:0] INMODE;
-    input MULTSIGNIN;
-    (* invertible_pin = "IS_OPMODE_INVERTED" *)
-    input [6:0] OPMODE;
-    input [47:0] PCIN;
-    input RSTA;
-    input RSTALLCARRYIN;
-    input RSTALUMODE;
-    input RSTB;
-    input RSTC;
-    input RSTCTRL;
-    input RSTD;
-    input RSTINMODE;
-    input RSTM;
-    input RSTP;
-endmodule
-
 module BUFGCE (...);
     parameter CE_TYPE = "SYNC";
     parameter [0:0] IS_CE_INVERTED = 1'b0;