techlibs/anlogic/drams.txt - third_party/yosys - Git at Google

 bram $__ANLOGIC_DRAM16X4
   init 0
   abits 4
   dbits 2
   groups 2
   ports  1 1
   wrmode 0 1
   enable 0 1
   transp 0 0
   clocks 0 1
   clkpol 0 1
 endbram

 match $__ANLOGIC_DRAM16X4
   make_outreg
 endmatch
	bram $__ANLOGIC_DRAM16X4
	init 0
	abits 4
	dbits 2
	groups 2
	ports 1 1
	wrmode 0 1
	enable 0 1
	transp 0 0
	clocks 0 1
	clkpol 0 1
	endbram

	match $__ANLOGIC_DRAM16X4
	make_outreg
	endmatch