blob: 160c767fb873c77310cf5ff8d1765ad163ef5eab [file]
read_verilog test_arith.v
synth_ice40
techmap -map ../cells_sim.v
rename test gate
read_verilog test_arith.v
rename test gold
miter -equiv -flatten -make_outputs gold gate miter
sat -verify -prove trigger 0 -show-ports miter