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foss-fpga-tools
/
third_party
/
yosys
/
a834cfa50ac9a22621691c9e3c6304e5faabef98
/
.
/
tests
/
opt
/
opt_lut.ys
blob: 59b12c3511544f7c20351948f0110e9606f686b5 [
file
]
read_verilog opt_lut
.
v
synth_ice40
ice40_unlut
equiv_opt
-
map
+
/ice40/
cells_sim
.
v
-
assert
opt_lut
-
dlogic SB_CARRY
:
I0
=
1
:
I1
=
2
:
CI
=
3
