tests/xilinx/latches.ys

read_verilog latches.v

proc
flatten
equiv_opt -assert -run :prove -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
async2sync
equiv_opt -assert -run prove: -map +/xilinx/cells_sim.v synth_xilinx # equivalency check

design -load preopt
synth_xilinx
cd top
select -assert-count 1 t:LUT1
select -assert-count 2 t:LUT3
select -assert-count 3 t:LDCE
select -assert-none t:LUT1 t:LUT3 t:LDCE %% t:* %D