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foss-fpga-tools
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/
yosys
/
b0c7ad96bfcd67d30e66e360f1e968aaa14b7ce6
/
.
/
manual
/
APPNOTE_011_Design_Investigation
/
splice.v
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module
splice_demo
(
a
,
b
,
c
,
d
,
e
,
f
,
x
,
y
);
input
[
1
:
0
]
a
,
b
,
c
,
d
,
e
,
f
;
output
[
1
:
0
]
x
=
{
a
[
0
],
a
[
1
]};
output
[
11
:
0
]
y
;
assign
{
y
[
11
:
4
],
y
[
1
:
0
],
y
[
3
:
2
]}
=
{
a
,
b
,
-{
c
,
d
},
~{
e
,
f
}};
endmodule
