Merge remote-tracking branch 'origin/xaig_dff' into eddie/exp
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index f17a4c7..e05b6cc 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc
@@ -184,7 +184,6 @@ if (bit != wirebit) alias_map[bit] = wirebit; input_bits.insert(wirebit); - undriven_bits.erase(bit); } if (wire->port_output || keep) { @@ -192,8 +191,6 @@ if (bit != wirebit) alias_map[wirebit] = bit; output_bits.insert(wirebit); - if (!wire->port_input) - unused_bits.erase(bit); } else log_debug("Skipping PO '%s' driven by 1'bx\n", log_signal(wirebit)); @@ -201,6 +198,12 @@ } } + // Cannot fold into above due to use of sigmap + for (auto bit : input_bits) + undriven_bits.erase(sigmap(bit)); + for (auto bit : output_bits) + unused_bits.erase(sigmap(bit)); + // TODO: Speed up toposort -- ultimately we care about // box ordering, but not individual AIG cells dict<SigBit, pool<IdString>> bit_drivers, bit_users;
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index b21b0de..839f856 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc
@@ -228,11 +228,16 @@ RTLIL::SigSpec old_sig = sigmap(it.first); RTLIL::Wire *new_wire = it.second.new_wire; if (new_wire->port_id > 0) { - // Prevents "ERROR: Mismatch in directionality ..." when flattening if (new_wire->port_output) - for (auto &b : old_sig) + for (int i = 0; i < GetSize(old_sig); i++) { + auto &b = old_sig[i]; + // Prevents "ERROR: Mismatch in directionality ..." when flattening if (!b.wire) b = module->addWire(NEW_ID); + // Prevents "Warning: multiple conflicting drivers ..." + else if (!it.second.is_int_driven[i]) + b = module->addWire(NEW_ID); + } new_cell->setPort(new_wire->name, old_sig); } }
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index 2c45670..f59f978 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc
@@ -83,7 +83,9 @@ bool operator==(const ExtSigSpec &other) const { return is_signed == other.is_signed && sign == other.sign && sig == other.sig && semantics == other.semantics; } }; -#define BITWISE_OPS ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($and), ID($or), ID($xor), ID($xnor) +#define FINE_BITWISE_OPS ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_) + +#define BITWISE_OPS FINE_BITWISE_OPS, ID($and), ID($or), ID($xor), ID($xnor) #define REDUCTION_OPS ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), ID($reduce_nand) @@ -250,14 +252,19 @@ shared_op->setPort(ID(CO), alu_co.extract(0, conn_width)); } - shared_op->setParam(ID(Y_WIDTH), conn_width); + bool is_fine = shared_op->type.in(FINE_BITWISE_OPS); + + if (!is_fine) + shared_op->setParam(ID(Y_WIDTH), conn_width); if (decode_port(shared_op, ID::A, &assign_map) == operand) { shared_op->setPort(ID::B, mux_to_oper); - shared_op->setParam(ID(B_WIDTH), max_width); + if (!is_fine) + shared_op->setParam(ID(B_WIDTH), max_width); } else { shared_op->setPort(ID::A, mux_to_oper); - shared_op->setParam(ID(A_WIDTH), max_width); + if (!is_fine) + shared_op->setParam(ID(A_WIDTH), max_width); } }
diff --git a/tests/opt/bug1525.ys b/tests/opt/bug1525.ys new file mode 100644 index 0000000..972bc0a --- /dev/null +++ b/tests/opt/bug1525.ys
@@ -0,0 +1,13 @@ +read_verilog << EOF +module top(...); +input A1, A2, B, S; +output O; + +assign O = S ? (A1 & B) : (A2 & B); + +endmodule +EOF + +simplemap +opt_share +dump
diff --git a/tests/various/submod.ys b/tests/various/submod.ys index 552fd4e..9d7dabd 100644 --- a/tests/various/submod.ys +++ b/tests/various/submod.ys
@@ -15,6 +15,7 @@ design -save gold submod +check -assert design -stash gate design -import gold -as gold @@ -41,6 +42,7 @@ design -save gold submod +check -assert top design -stash gate design -import gold -as gold @@ -51,6 +53,35 @@ design -reset +read_verilog <<EOT +module top(input a, output [1:0] b, c); +(* submod="bar" *) sub s1(a, b[0]); +(* submod="bar" *) sub s2(a, c[1]); +assign c = b; +endmodule + +module sub(input a, output c); +assign c = a; +endmodule +EOT + +hierarchy -top top +proc +design -save gold + +submod +check -assert top +design -stash gate + +design -import gold -as gold +design -import gate -as gate + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + + + +design -reset read_verilog -icells <<EOT module top(input d, c, (* init = 3'b011 *) output reg [2:0] q); (* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q[1]));