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yosys
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b4ac539f48d1370133f2aa72d0df9ccd02a66d84
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.
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manual
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PRESENTATION_ExSyn
/
proc_03.v
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module
test
(
input A
,
B
,
C
,
D
,
E
,
output reg Y
);
always
@*
begin
Y
<=
A
;
if
(
B
)
Y
<=
C
;
if
(
D
)
Y
<=
E
;
end
endmodule
