| # read design | |
| read_verilog counter.v | |
| hierarchy -check -top counter | |
| show -notitle -stretch -format pdf -prefix counter_00 | |
| # the high-level stuff | |
| proc; opt; memory; opt; fsm; opt | |
| show -notitle -stretch -format pdf -prefix counter_01 | |
| # mapping to internal cell library | |
| techmap; opt | |
| splitnets -ports;; | |
| show -notitle -stretch -format pdf -prefix counter_02 | |
| # mapping flip-flops to mycells.lib | |
| dfflibmap -liberty mycells.lib | |
| # mapping logic to mycells.lib | |
| abc -liberty mycells.lib | |
| # cleanup | |
| clean | |
| show -notitle -stretch -lib mycells.v -format pdf -prefix counter_03 |