tests/opt/bug1525.ys - third_party/yosys - Git at Google

 read_verilog << EOF
 module top(...);
 input A1, A2, B, S;
 output O;

 assign O = S ? (A1 & B) : (A2 & B);

 endmodule
 EOF

 simplemap
 opt_share
 dump
	read_verilog << EOF
	module top(...);
	input A1, A2, B, S;
	output O;

	assign O = S ? (A1 & B) : (A2 & B);

	endmodule
	EOF

	simplemap
	opt_share
	dump