| read_verilog ../common/memory.v | |
| hierarchy -top top | |
| proc | |
| memory -nomap | |
| equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5 | |
| memory | |
| opt -full | |
| miter -equiv -flatten -make_assert -make_outputs gold gate miter | |
| sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter | |
| design -load postopt | |
| cd top | |
| select -assert-count 24 t:L6MUX21 | |
| select -assert-count 71 t:LUT4 | |
| select -assert-count 32 t:PFUMX | |
| select -assert-count 8 t:TRELLIS_DPR16X4 | |
| select -assert-count 35 t:TRELLIS_FF | |
| select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D |