| read_verilog ../common/memory.v | |
| hierarchy -top top | |
| proc | |
| memory -nomap | |
| equiv_opt -run :prove -map +/gowin/cells_sim.v synth_gowin | |
| memory | |
| opt -full | |
| miter -equiv -flatten -make_assert -make_outputs gold gate miter | |
| #ERROR: Called with -verify and proof did fail! | |
| #sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter | |
| sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter | |
| design -load postopt | |
| cd top | |
| select -assert-count 8 t:RAM16S4 | |
| # other logic present that is not simple | |
| #select -assert-none t:RAM16S4 %% t:* %D |