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foss-fpga-tools
/
third_party
/
yosys
/
f90a4b1e24e36943a343bd36315b6029dd6cd044
/
.
/
examples
/
osu035
/
example.v
blob: 0f043e5fc1e3df4b779c59b80773f016d73a0dd1 [
file
]
module
top
(
input clk
,
input
[
7
:
0
]
a
,
b
,
output reg
[
15
:
0
]
c
);
always
@(
posedge clk
)
c
<=
a
*
b
;
endmodule
