| # read test design | |
| read_verilog ../PRESENTATION_ExSyn/techmap_01.v | |
| hierarchy -top test | |
| # create two version of the design: test_orig and test_mapped | |
| copy test test_orig | |
| rename test test_mapped | |
| # apply the techmap only to test_mapped | |
| techmap -map ../PRESENTATION_ExSyn/techmap_01_map.v test_mapped | |
| # create a miter circuit to test equivalence | |
| miter -equiv -make_assert -make_outputs test_orig test_mapped miter | |
| flatten miter | |
| # run equivalence check | |
| sat -verify -prove-asserts -show-inputs -show-outputs miter |