| read_verilog ../common/dffs.v |
| design -save read |
| |
| hierarchy -top dff |
| proc |
| equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check |
| design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) |
| cd dff # Constrain all select calls below inside the top module |
| select -assert-count 1 t:BUFG |
| select -assert-count 1 t:FDRE |
| |
| select -assert-none t:BUFG t:FDRE %% t:* %D |
| |
| |
| design -load read |
| hierarchy -top dffe |
| proc |
| equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check |
| design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) |
| cd dffe # Constrain all select calls below inside the top module |
| select -assert-count 1 t:BUFG |
| select -assert-count 1 t:FDRE |
| |
| select -assert-none t:BUFG t:FDRE %% t:* %D |
| |
