passes/pmgen/xilinx_dff.pmg

pattern xilinx_dff

match fd
	select fd->type.in(\FDRE)
	select port(fd, \R).is_fully_zero()
	select port(fd, \CE).is_fully_ones()
endmatch

match lut
	select lut->type.in(\LUT2)
	index <SigSpec> port(lut, \O) === port(fd, \D)
endmatch

code
	if (lut->type == \LUT2) {
		if (param(lut, \INIT) == Const::from_string("0010")) {
			fd->setPort(\D, port(lut, \I0));
			fd->setPort(\R, port(lut, \I1));
		}
		else if (param(lut, \INIT) == Const::from_string("0100")) {
			fd->setPort(\R, port(lut, \I0));
			fd->setPort(\D, port(lut, \I1));
		}
	}
	else log_abort();
endcode