| |
| \chapter{Application Notes} |
| \label{chapter:appnotes} |
| |
| % \begin{fixme} |
| % This appendix will cover some typical use-cases of Yosys in the form of application notes. |
| % \end{fixme} |
| % |
| % \section{Synthesizing using a Cell Library in Liberty Format} |
| % \section{Reverse Engineering the MOS6502 from an NMOS Transistor Netlist} |
| % \section{Reconfigurable Coarse-Grain Synthesis using Intersynth} |
| |
| This appendix contains copies of the Yosys application notes. |
| |
| \begin{itemize} |
| \item Yosys AppNote 010: Converting Verilog to BLIF \dotfill Page \pageref{app:010} \hskip2cm\null |
| \item Yosys AppNote 011: Interactive Design Investigation \dotfill Page \pageref{app:011} \hskip2cm\null |
| \item Yosys AppNote 012: Converting Verilog to BTOR \dotfill Page \pageref{app:012} \hskip2cm\null |
| \end{itemize} |
| |
| \eject\label{app:010} |
| \includepdf[pages=-,pagecommand=\thispagestyle{plain}]{APPNOTE_010_Verilog_to_BLIF.pdf} |
| |
| \eject\label{app:011} |
| \includepdf[pages=-,pagecommand=\thispagestyle{plain}]{APPNOTE_011_Design_Investigation.pdf} |
| |
| \eject\label{app:012} |
| \includepdf[pages=-,pagecommand=\thispagestyle{plain}]{APPNOTE_012_Verilog_to_BTOR.pdf} |
| |
