| read_verilog ../common/fsm.v |
| hierarchy -top fsm |
| proc |
| flatten |
| |
| equiv_opt -run :prove -map +/efinix/cells_sim.v synth_efinix |
| miter -equiv -make_assert -flatten gold gate miter |
| sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter |
| |
| design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) |
| cd fsm # Constrain all select calls below inside the top module |
| |
| select -assert-count 1 t:EFX_GBUFCE |
| select -assert-count 6 t:EFX_FF |
| select -assert-count 15 t:EFX_LUT4 |
| select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D |
