| read_verilog ../common/shifter.v | |
| hierarchy -top top | |
| proc | |
| flatten | |
| equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check | |
| design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) | |
| cd top # Constrain all select calls below inside the top module | |
| select -assert-count 1 t:BUFG | |
| select -assert-count 8 t:FDRE | |
| select -assert-none t:BUFG t:FDRE %% t:* %D |