| read_verilog counters-repeat.v | |
| proc; opt | |
| expose -shared counter1 counter2 | |
| miter -equiv -make_assert -make_outputs counter1 counter2 miter | |
| cd miter; flatten; opt | |
| sat -verify -prove-asserts -tempinduct -set-at 1 in_rst 1 -seq 1 -show-inputs -show-outputs | |