tests/various/bug1462.ys - third_party/yosys - Git at Google

 read_verilog << EOF
 module top(...);
 input wire [31:0] A;
 output wire [31:0] P;

 assign P = A * 32'h12300000;

 endmodule
 EOF

 synth_xilinx
	read_verilog << EOF
	module top(...);
	input wire [31:0] A;
	output wire [31:0] P;

	assign P = A * 32'h12300000;

	endmodule
	EOF

	synth_xilinx