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foss-fpga-tools
/
third_party
/
yosys
/
refs/heads/mwk/xilinx-clb-sim
/
.
/
backends
/
smt2
/
example.v
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module
main
(
input clk
);
reg
[
3
:
0
]
counter
=
0
;
always
@(
posedge clk
)
begin
if
(
counter
==
10
)
counter
<=
0
;
else
counter
<=
counter
+
1
;
end
assert
property
(
counter
!=
15
);
// assert property (counter <= 10);
endmodule