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foss-fpga-tools
/
third_party
/
yosys
/
refs/heads/mwk/xilinx-clb-sim
/
.
/
techlibs
/
achronix
/
Makefile.inc
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OBJS
+=
techlibs
/
achronix
/
synth_achronix
.
o
$
(
eval
$
(
call add_share_file
,
share
/
achronix
/
speedster22i
/,
techlibs
/
achronix
/
speedster22i
/
cells_sim
.
v
))
$
(
eval
$
(
call add_share_file
,
share
/
achronix
/
speedster22i
/,
techlibs
/
achronix
/
speedster22i
/
cells_map
.
v
))
