manual/CHAPTER_StateOfTheArt/always01_pub.v - third_party/yosys - Git at Google

 module uut_always01(clock,
 		reset, count);

 input clock, reset;
 output [3:0] count;
 reg [3:0] count;

 always @(posedge clock)
 	count <= reset ?
 		0 : count + 1;


 endmodule
	module uut_always01(clock,
	reset, count);

	input clock, reset;
	output [3:0] count;
	reg [3:0] count;

	always @(posedge clock)
	count <= reset ?
	0 : count + 1;



	endmodule