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foss-fpga-tools
/
third_party
/
yosys
/
refs/heads/mwk/xilinx-dff-improvements
/
.
/
manual
/
PRESENTATION_ExAdv
/
addshift_test.v
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module
test
(
A
,
B
,
X
,
Y
);
input
[
7
:
0
]
A
,
B
;
output
[
7
:
0
]
X
=
A
+
B
;
output
[
7
:
0
]
Y
=
A
+
A
;
endmodule
