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foss-fpga-tools
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third_party
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yosys
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refs/heads/mwk/xilinx-dff-improvements
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.
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manual
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PRESENTATION_ExSyn
/
opt_02.v
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module
test
(
input A
,
output Y
,
Z
);
assign Y
=
A
==
A
,
Z
=
A
!=
A
;
endmodule
