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foss-fpga-tools
/
third_party
/
yosys
/
refs/heads/mwk/xilinx-dff-improvements
/
.
/
techlibs
/
greenpak4
/
cells_latch.v
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module
$_DLATCH_P_
(
input E
,
input D
,
output Q
);
GP_DLATCH _TECHMAP_REPLACE_
(
.
D
(
D
),
.
nCLK
(!
E
),
.
Q
(
Q
)
);
endmodule
module
$_DLATCH_N_
(
input E
,
input D
,
output Q
);
GP_DLATCH _TECHMAP_REPLACE_
(
.
D
(
D
),
.
nCLK
(
E
),
.
Q
(
Q
)
);
endmodule
