| read_verilog ../common/counter.v |
| hierarchy -top top |
| proc |
| flatten |
| equiv_opt -map +/gowin/cells_sim.v synth_gowin # equivalency check |
| design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) |
| cd top # Constrain all select calls below inside the top module |
| |
| select -assert-count 8 t:DFFC |
| select -assert-count 8 t:ALU |
| select -assert-count 1 t:GND |
| select -assert-count 1 t:VCC |
| select -assert-count 2 t:IBUF |
| select -assert-count 8 t:OBUF |
| select -assert-none t:DFFC t:ALU t:GND t:VCC t:IBUF t:OBUF %% t:* %D |
