tests/arch/ice40/logic.ys - third_party/yosys - Git at Google

 read_verilog ../common/logic.v
 hierarchy -top top
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 9 t:SB_LUT4
 select -assert-none t:SB_LUT4 %% t:* %D
	read_verilog ../common/logic.v
	hierarchy -top top
	equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
	design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
	cd top # Constrain all select calls below inside the top module
	select -assert-count 9 t:SB_LUT4
	select -assert-none t:SB_LUT4 %% t:* %D