| read_verilog ../common/counter.v |
| hierarchy -top top |
| proc |
| flatten |
| equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check |
| design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) |
| cd top # Constrain all select calls below inside the top module |
| |
| select -assert-count 1 t:BUFG |
| select -assert-count 8 t:FDCE |
| select -assert-count 1 t:INV |
| select -assert-count 7 t:MUXCY |
| select -assert-count 8 t:XORCY |
| select -assert-none t:BUFG t:FDCE t:INV t:MUXCY t:XORCY %% t:* %D |
