| read_verilog ../common/fsm.v |
| hierarchy -top fsm |
| proc |
| flatten |
| |
| equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx |
| miter -equiv -make_assert -flatten gold gate miter |
| sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter |
| |
| design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) |
| cd fsm # Constrain all select calls below inside the top module |
| |
| select -assert-count 1 t:BUFG |
| select -assert-count 4 t:FDRE |
| select -assert-count 1 t:FDSE |
| select -assert-count 1 t:LUT2 |
| select -assert-count 2 t:LUT3 |
| select -assert-count 4 t:LUT5 |
| select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT3 t:LUT5 %% t:* %D |
