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foss-fpga-tools
/
third_party
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yosys
/
refs/heads/mwk/xilinx-dff-improvements
/
.
/
tests
/
errors
/
syntax_err07.v
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module
a
;
wire
[
5
:
0
]
x
;
wire
[
3
:
0
]
y
;
assign y
=
(
4
)
55
;
endmodule
