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foss-fpga-tools
/
third_party
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yosys
/
refs/heads/mwk/xilinx-dff-improvements
/
.
/
tests
/
simple
/
param_attr.v
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module
uut_param_attr
(
I
,
O
);
(*
PARAMETER_ATTRIBUTE
=
"attribute_content"
*)
parameter WIDTH
=
1
;
input wire
[
WIDTH
-
1
:
0
]
I
;
output wire
[
WIDTH
-
1
:
0
]
O
;
assign O
=
I
;
endmodule
