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yosys
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refs/heads/mwk/xilinx-dff-improvements
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tests
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various
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equiv_opt_multiclock.ys
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read_verilog
<<
EOT
module
top
(
input clk
,
pre
,
d
,
output reg q
);
always
@(
posedge clk
,
posedge pre
)
if
(
pre
)
q
<=
1
'b1;
else
q <= d;
endmodule
EOT
prep
equiv_opt -assert -multiclock -map +/simcells.v synth
