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foss-fpga-tools/third_party/yosys/HEAD
  1. 5f4c35c Merge pull request #1540 from YosysHQ/mwk/xilinx-bufpll by Miodrag Milanović · 7 years ago master
  2. 2badaa9 xilinx: Add missing blackbox cell for BUFPLL. by Marcin Kościelnicki · 7 years ago mwk/xilinx-bufpll
  3. 419ca5c Revert "Fold loop" by Eddie Hung · 7 years ago
  4. 6464dc3 Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd by Eddie Hung · 7 years ago
  5. 41e0ddf Merge pull request #1501 from YosysHQ/dave/mem_copy_attr by Clifford Wolf · 7 years ago
  6. f43c0bd Merge pull request #1534 from YosysHQ/mwk/opt_share-fix by Clifford Wolf · 7 years ago
  7. 95053d9 Merge pull request #1535 from YosysHQ/eddie/write_xaiger_improve by Eddie Hung · 7 years ago
  8. de3476c No need for -abc9 by Eddie Hung · 7 years ago
  9. fdcbda1 opt_share: Fix handling of fine cells. by Marcin Kościelnicki · 7 years ago
  10. 5e67df3 latch -> box by Eddie Hung · 7 years ago
  11. 4a01981 Add citation by Eddie Hung · 7 years ago
  12. 2105ae1 Check for either sign or zero extension for postAdd packing by Eddie Hung · 7 years ago
  13. 15042ea Remove notes by Eddie Hung · 7 years ago
  14. a30d5e1 Fold loop by Eddie Hung · 7 years ago
  15. 68717dd Do not sigmap keep bits inside write_xaiger by Eddie Hung · 7 years ago
  16. 7136cee xaiger: do not promote output wires by Eddie Hung · 7 years ago
  17. 222e199 Add testcase derived from fastfir_dynamictaps benchmark by Eddie Hung · 7 years ago
  18. 0466c48 xilinx: Add simulation models for IOBUF and OBUFT. by Marcin Kościelnicki · 7 years ago
  19. 6cdea42 clkbufmap: Add support for inverters in clock path. by Marcin Kościelnicki · 7 years ago
  20. 7562e73 xilinx: Use INV instead of LUT1 when applicable by Marcin Kościelnicki · 7 years ago
  21. db22687 Merge pull request #1520 from pietrmar/fix-1463 by Eddie Hung · 7 years ago
  22. 97b2241 coolrunner2: remove spurious log_pop() call, fixes #1463 by Martin Pietryka · 7 years ago
  23. c03b6a3 Merge pull request #1517 from YosysHQ/clifford/optmem by Clifford Wolf · 7 years ago
  24. caa3b21 Merge pull request #1515 from YosysHQ/clifford/svastuff by Clifford Wolf · 7 years ago
  25. 03fb92e Add "opt_mem" pass by Clifford Wolf · 7 years ago
  26. db32368 Add Verific support for SVA nexttime properties by Clifford Wolf · 7 years ago
  27. e93e4a7 Improve handling of verific primitives in "verific -import -V" mode by Clifford Wolf · 7 years ago
  28. 6af0d03 Add Verific SVA support for "always" properties by Clifford Wolf · 7 years ago
  29. 72d2ef6 Merge pull request #1511 from YosysHQ/dave/always by Clifford Wolf · 7 years ago
  30. e110df9 gowin: Remove show command from tests. by Marcin Kościelnicki · 7 years ago
  31. 1d098b7 gowin: Add missing .gitignore entries by Marcin Kościelnicki · 7 years ago
  32. b60f32c Update CHANGELOG and README by David Shah · 7 years ago
  33. 49b670c sv: Add tests for SV always types by David Shah · 7 years ago
  34. ca99b1e proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usage by David Shah · 7 years ago
  35. 9e4801c sv: Correct parsing of always_comb, always_ff and always_latch by David Shah · 7 years ago
  36. 0ac330b Merge pull request #1507 from YosysHQ/clifford/verificfixes by Clifford Wolf · 7 years ago
  37. 55bda2b Correctly treat empty modules as blackboxes in Verific by Clifford Wolf · 7 years ago
  38. f6ff311 Do not rename VHDL entities to "entity(impl)" when they are top modules by Clifford Wolf · 7 years ago
  39. 7ea0a59 Merge pull request #1449 from pepijndevos/gowin by Clifford Wolf · 7 years ago
  40. 8ab412e Remove dff init altogether by Pepijn de Vos · 7 years ago
  41. 15232a4 Fix #1462, #1480. by Marcin Kościelnicki · 7 years ago
  42. 7a90814 xilinx: Add simulation models for MULT18X18* and DSP48A*. by Marcin Kościelnicki · 7 years ago
  43. 7ff5d6d memory_collect: Copy attr from RTLIL::Memory to cell by David Shah · 7 years ago
  44. dd8c7e1 add help for nowidelut and abc9 options by Pepijn de Vos · 7 years ago
  45. 9ee3c57 Merge pull request #1497 from YosysHQ/mwk/extract-fa-fix by Clifford Wolf · 7 years ago
  46. cdb566b Merge pull request #1494 from whitequark/write_verilog-extmem by whitequark · 7 years ago
  47. 38e72d6 Fix #1496. by Marcin Kościelnicki · 7 years ago
  48. 3c643c5 write_verilog: add -extmem option, to write split memory init files. by whitequark · 7 years ago
  49. 527434d Merge pull request #1492 from YosysHQ/dave/wreduce-fix-arst by Clifford Wolf · 7 years ago
  50. 32f0296 Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin by Pepijn de Vos · 7 years ago
  51. 51e4e29 ecp5: Use new autoname pass for better cell/net names by David Shah · 7 years ago
  52. f5804a8 wreduce: Don't trim zeros or sext when not matching ARST_VALUE by David Shah · 7 years ago
  53. e907ee4 Merge pull request #1490 from YosysHQ/clifford/autoname by Clifford Wolf · 7 years ago
  54. 4b18a45 Merge pull request #1444 from btut/feature/python_wrappers/globals_and_streams by Clifford Wolf · 7 years ago
  55. 056ef76 Merge pull request #1465 from YosysHQ/dave/ice40_timing_sim by Clifford Wolf · 7 years ago
  56. f453f57 Merge branch 'makaimann-label-bads-btor' by Clifford Wolf · 7 years ago
  57. cd44826 Use cell name for btor bad state props when it is a public name by Clifford Wolf · 7 years ago
  58. 89834b9 Merge branch 'label-bads-btor' of https://github.com/makaimann/yosys into makaimann-label-bads-btor by Clifford Wolf · 7 years ago
  59. 07c854b Add "autoname" pass and use it in "synth_ice40" by Clifford Wolf · 7 years ago
  60. ab0fb19 Merge pull request #1488 from whitequark/flowmap-fixes by whitequark · 7 years ago
  61. 6e33216 Merge pull request #1486 from YosysHQ/clifford/fsmdetectfix by Clifford Wolf · 7 years ago
  62. 4be5a0f Update fsm_detect bugfix by Clifford Wolf · 7 years ago
  63. 16df8f5 Bugfix in fsm_detect by Clifford Wolf · 7 years ago
  64. e0ba78b Merge pull request #1484 from YosysHQ/clifford/cmp2luteqne by Clifford Wolf · 7 years ago
  65. d88cc13 Add an info string symbol for bad states in btor backend by Makai Mann · 7 years ago
  66. c687228 flowmap: when doing mincut, ensure source is always in X, not X̅. by whitequark · 7 years ago
  67. eef3219 flowmap: don't break if that creates a k+2 (and larger) LUT either. by whitequark · 7 years ago
  68. ab8c521 fix fsm test with proper clock enable polarity by Pepijn de Vos · 7 years ago
  69. ec3faa7 Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin by Pepijn de Vos · 7 years ago
  70. 3e0ffe0 Fixed tests by Miodrag Milanovic · 7 years ago
  71. 362f4f9 Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp by Clifford Wolf · 7 years ago
  72. 1d14849 Merge pull request #1470 from YosysHQ/clifford/subpassdoc by Clifford Wolf · 7 years ago
  73. 65f197e Add check for valid macro names in macro definitions by Clifford Wolf · 7 years ago
  74. 0e5dbc4 fix wide luts by Pepijn de Vos · 7 years ago
  75. c4bd318 synth_xilinx: Merge blackbox primitive libraries. by Marcin Kościelnicki · 7 years ago
  76. 5110a34 Fix write_aiger bug added in 524af21 by Clifford Wolf · 7 years ago
  77. c3ad375 Add CodingReadme section on script passes by Clifford Wolf · 7 years ago
  78. df8390f don't cound exact luts in big muxes; futile and fragile by Pepijn de Vos · 7 years ago
  79. 0f6269b add IOBUF by Pepijn de Vos · 7 years ago
  80. 903f997 add tristate buffer and test by Pepijn de Vos · 7 years ago
  81. 9517525 do not use wide luts in testcase by Pepijn de Vos · 7 years ago
  82. 4ec4d5e actually run the gowin tests by Pepijn de Vos · 7 years ago
  83. 2f5e9e9 More formatting by Pepijn de Vos · 7 years ago
  84. c1921b4 really really fix formatting maybe by Pepijn de Vos · 7 years ago
  85. 293b2c2 undo formatting fuckup by Pepijn de Vos · 7 years ago
  86. f88335a add wide luts by Pepijn de Vos · 7 years ago
  87. 5fad53b add 32-bit BRAM and byte-enables by Pepijn de Vos · 7 years ago
  88. 81876a3 Merge pull request #1393 from whitequark/write_verilog-avoid-init by Clifford Wolf · 7 years ago
  89. 8226f2d ALU sim tweaks by Pepijn de Vos · 7 years ago
  90. 84982b3 Improve naming scheme for (VHDL) modules imported from Verific by Clifford Wolf · 7 years ago
  91. 34dadd9 Merge pull request #1455 from YosysHQ/dave/ultrascaleplus by David Shah · 7 years ago
  92. d49c6b2 Add "verific -L" by Clifford Wolf · 7 years ago
  93. e135ed5 ice40: Add post-pnr ICESTORM_RAM model and fix FFs by David Shah · 7 years ago
  94. 37dd3ad ice40: Support for post-pnr timing simulation by David Shah · 7 years ago
  95. 3506eaf xilinx: Add URAM288 mapping for xcup by David Shah · 7 years ago
  96. 6769d31 xilinx: Add support for UltraScale[+] BRAM mapping by David Shah · 7 years ago
  97. f02623a Bugfix in smtio vcd handling of $-identifiers by Clifford Wolf · 7 years ago
  98. 7b350ca xilinx: Support multiplier mapping for all families. by Marcin Kościelnicki · 7 years ago
  99. a3a7bb9 Merge pull request #1452 from nakengelhardt/fix_dsp_mem_reg by Clifford Wolf · 7 years ago
  100. 83fbfe0 Add some tests by Pepijn de Vos · 7 years ago