Add missing power and clocks elements.
Added sb_loc elements.
Changed pb_type io equivalent to match definitions uses in VPR archdefs.
Made fs in switch_block optional, as it can be for custom switch_blocks.
Added device_layout as an alias for fixed_layout.

Signed-off-by: Jeppe Johansen <jeppe@j-software.dk>
1 file changed
tree: 1a1b7f5625b8f6caa3f7405bcc0342922f8f2b72
  1. .gitignore/
  2. vtr_xml_utils/
  3. CODE_OF_CONDUCT.md
  4. CONTRIBUTING.md
  5. COPYING
  6. fpga_architecture.xsd
  7. packed_netlist.xsd
  8. README.md
  9. routing_resource.xsd
  10. setup.cfg
  11. setup.py
  12. xmlsort.xsl
README.md

Utilities for working with VtR XML Files

This repository contains utilities for working with Verilog to Routing XML files.