Add missing power and clocks elements. Added sb_loc elements. Changed pb_type io equivalent to match definitions uses in VPR archdefs. Made fs in switch_block optional, as it can be for custom switch_blocks. Added device_layout as an alias for fixed_layout. Signed-off-by: Jeppe Johansen <jeppe@j-software.dk>
This repository contains utilities for working with Verilog to Routing XML files.