SDC: Clang format Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
diff --git a/sdc-plugin/buffers.cc b/sdc-plugin/buffers.cc index ba8fd81..072efe1 100644 --- a/sdc-plugin/buffers.cc +++ b/sdc-plugin/buffers.cc
@@ -18,6 +18,7 @@ #include "buffers.h" const std::vector<std::string> Pll::inputs = {"CLKIN1", "CLKIN2"}; -const std::vector<std::string> Pll::outputs = {"CLKOUT0", "CLKOUT1", "CLKOUT2", "CLKOUT3", "CLKOUT4", "CLKOUT5"}; +const std::vector<std::string> Pll::outputs = {"CLKOUT0", "CLKOUT1", "CLKOUT2", + "CLKOUT3", "CLKOUT4", "CLKOUT5"}; const float Pll::delay = 1; const std::string Pll::name = "PLLE2_ADV";
diff --git a/sdc-plugin/clocks.cc b/sdc-plugin/clocks.cc index d7056c1..c7f6e9d 100644 --- a/sdc-plugin/clocks.cc +++ b/sdc-plugin/clocks.cc
@@ -21,16 +21,16 @@ #include "kernel/register.h" #include "propagation.h" -void Clocks::AddClock(const std::string& name, - std::vector<RTLIL::Wire*> wires, float period, - float rising_edge, float falling_edge) { +void Clocks::AddClock(const std::string& name, std::vector<RTLIL::Wire*> wires, + float period, float rising_edge, float falling_edge) { AddClockWires(name, wires, period, rising_edge, falling_edge); } -void Clocks::AddClock(const std::string& name, - RTLIL::Wire* wire, float period, - float rising_edge, float falling_edge) { - auto clock = std::find_if(clocks_.begin(), clocks_.end(), [&](Clock& clock) { return clock.Name() == name; }); +void Clocks::AddClock(const std::string& name, RTLIL::Wire* wire, float period, + float rising_edge, float falling_edge) { + auto clock = + std::find_if(clocks_.begin(), clocks_.end(), + [&](Clock& clock) { return clock.Name() == name; }); if (clock != clocks_.end()) { log("Clock %s already exists and will be overwritten\n", name.c_str()); clocks_.erase(clock); @@ -39,7 +39,8 @@ } void Clocks::AddClock(Clock& clock) { - AddClock(clock.Name(), clock.GetClockWires(), clock.Period(), clock.RisingEdge(), clock.FallingEdge()); + AddClock(clock.Name(), clock.GetClockWires(), clock.Period(), + clock.RisingEdge(), clock.FallingEdge()); } void Clocks::AddClockWires(const std::string& name, @@ -52,11 +53,13 @@ void Clocks::AddClockWire(const std::string& name, RTLIL::Wire* wire, float period, float rising_edge, float falling_edge) { - auto clock = std::find_if(clocks_.begin(), clocks_.end(), [&](Clock& clock) { return clock.Name() == name; }); + auto clock = + std::find_if(clocks_.begin(), clocks_.end(), + [&](Clock& clock) { return clock.Name() == name; }); if (clock == clocks_.end()) { AddClock(name, wire, period, rising_edge, falling_edge); } else { - clock->AddWire(wire); + clock->AddWire(wire); } } @@ -70,8 +73,8 @@ ss << RTLIL::unescape_id(clock_wire->name) << " "; } log("create_clock -period %f -name %s -waveform {%f %f} %s\n", - clock.Period(), clock.Name().c_str(), - clock.RisingEdge(), clock.FallingEdge(), ss.str().c_str()); + clock.Period(), clock.Name().c_str(), clock.RisingEdge(), + clock.FallingEdge(), ss.str().c_str()); } #endif return res; @@ -123,8 +126,8 @@ #endif auto clock_wires = clock.GetClockWires(); for (auto clock_wire : clock_wires) { - auto pll_clocks = pass->FindSinkClocksForCellType( - clock_wire, "PLLE2_ADV"); + auto pll_clocks = + pass->FindSinkClocksForCellType(clock_wire, "PLLE2_ADV"); for (auto pll_clock : pll_clocks) { #ifdef SDC_DEBUG log("PLL clock: %s\n", pll_clock.Name().c_str()); @@ -138,23 +141,23 @@ #endif } -void Clocks::PropagateThroughBuffer(BufferPropagation* pass, - Clock& clock, +void Clocks::PropagateThroughBuffer(BufferPropagation* pass, Clock& clock, Buffer buffer) { auto clock_wires = clock.GetClockWires(); for (auto clock_wire : clock_wires) { log("%s\n", clock_wire->name.c_str()); - auto buf_wires = pass->FindSinkWiresForCellType( - clock_wire, buffer.name, buffer.output); + auto buf_wires = pass->FindSinkWiresForCellType(clock_wire, buffer.name, + buffer.output); int path_delay(0); for (auto wire : buf_wires) { #ifdef SDC_DEBUG - log("%s wire: %s\n", buffer.name.c_str(), RTLIL::unescape_id(wire->name).c_str()); + log("%s wire: %s\n", buffer.name.c_str(), + RTLIL::unescape_id(wire->name).c_str()); #endif path_delay += buffer.delay; AddClock(RTLIL::unescape_id(wire->name), wire, clock.Period(), - clock.RisingEdge() + path_delay, - clock.FallingEdge() + path_delay); + clock.RisingEdge() + path_delay, + clock.FallingEdge() + path_delay); } } } @@ -166,9 +169,10 @@ if (clock_wires.size() > 1) { file << " -name " << clock.Name(); } - file << " -waveform {" << clock.RisingEdge() << " " << clock.FallingEdge() << "}"; + file << " -waveform {" << clock.RisingEdge() << " " + << clock.FallingEdge() << "}"; for (auto clock_wire : clock_wires) { - file << " " << RTLIL::unescape_id(clock_wire->name); + file << " " << RTLIL::unescape_id(clock_wire->name); } file << std::endl; } @@ -189,15 +193,12 @@ period_(period), rising_edge_(rising_edge), falling_edge_(falling_edge) { - std::for_each(wires.begin(), wires.end(), [&, this](RTLIL::Wire* wire) { - AddWire(wire); - }); + std::for_each(wires.begin(), wires.end(), + [&, this](RTLIL::Wire* wire) { AddWire(wire); }); } void Clock::AddWire(RTLIL::Wire* wire) { - auto clock_wire = std::find( - clock_wires_.begin(), clock_wires_.end(), - wire); + auto clock_wire = std::find(clock_wires_.begin(), clock_wires_.end(), wire); if (clock_wire == clock_wires_.end()) { clock_wires_.push_back(wire); }
diff --git a/sdc-plugin/propagation.cc b/sdc-plugin/propagation.cc index e8a519e..35e86f3 100644 --- a/sdc-plugin/propagation.cc +++ b/sdc-plugin/propagation.cc
@@ -15,8 +15,8 @@ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ -#include <cassert> #include "propagation.h" +#include <cassert> USING_YOSYS_NAMESPACE @@ -37,8 +37,8 @@ return alias_wires; } -std::vector<Clock> ClockDividerPropagation::FindSinkClocksForCellType(RTLIL::Wire* driver_wire, - const std::string& cell_type) { +std::vector<Clock> ClockDividerPropagation::FindSinkClocksForCellType( + RTLIL::Wire* driver_wire, const std::string& cell_type) { std::vector<Clock> clocks; if (cell_type == "PLLE2_ADV") { RTLIL::Cell* cell = NULL; @@ -56,11 +56,13 @@ RTLIL::Wire* wire = FindSinkWireOnPort(cell, output); if (wire) { float period(pll.CalculatePeriod(output)); - Clock clock(RTLIL::unescape_id(wire->name), wire, period, 0, period / 2); + Clock clock(RTLIL::unescape_id(wire->name), wire, period, 0, + period / 2); clocks.push_back(clock); - auto further_clocks = FindSinkClocksForCellType(wire, cell_type); + auto further_clocks = + FindSinkClocksForCellType(wire, cell_type); std::copy(further_clocks.begin(), further_clocks.end(), - std::back_inserter(clocks)); + std::back_inserter(clocks)); } } } @@ -86,14 +88,16 @@ if (selected_cells.size() > 0) { sink_cell = selected_cells.at(0); #ifdef SDC_DEBUG - log("Found sink cell: %s\n", RTLIL::unescape_id(sink_cell->name).c_str()); + log("Found sink cell: %s\n", + RTLIL::unescape_id(sink_cell->name).c_str()); #endif } return sink_cell; } -std::vector<RTLIL::Wire*> Propagation::FindSinkWiresForCellType(RTLIL::Wire* driver_wire, - const std::string& cell_type, const std::string& cell_port) { +std::vector<RTLIL::Wire*> Propagation::FindSinkWiresForCellType( + RTLIL::Wire* driver_wire, const std::string& cell_type, + const std::string& cell_port) { std::vector<RTLIL::Wire*> wires; if (!driver_wire) { return wires; @@ -102,7 +106,8 @@ RTLIL::Wire* wire = FindSinkWireOnPort(cell, cell_port); if (wire) { wires.push_back(wire); - auto further_wires = FindSinkWiresForCellType(wire, cell_type, cell_port); + auto further_wires = + FindSinkWiresForCellType(wire, cell_type, cell_port); std::copy(further_wires.begin(), further_wires.end(), std::back_inserter(wires)); } @@ -119,23 +124,25 @@ assert(top_module); std::string base_selection = top_module->name.str() + "/w:" + wire->name.str(); - pass_->extra_args(std::vector<std::string>{base_selection, "%co:+[" + port +"]", - base_selection, "%d"}, - 0, design_); + pass_->extra_args( + std::vector<std::string>{base_selection, "%co:+[" + port + "]", + base_selection, "%d"}, + 0, design_); auto selected_cells = top_module->selected_cells(); // FIXME Handle more than one sink assert(selected_cells.size() <= 1); if (selected_cells.size() > 0) { sink_cell = selected_cells.at(0); #ifdef SDC_DEBUG - log("Found sink cell: %s\n", RTLIL::unescape_id(sink_cell->name).c_str()); + log("Found sink cell: %s\n", + RTLIL::unescape_id(sink_cell->name).c_str()); #endif } return sink_cell; } -RTLIL::Wire* Propagation::FindSinkWireOnPort( - RTLIL::Cell* cell, const std::string& port_name) { +RTLIL::Wire* Propagation::FindSinkWireOnPort(RTLIL::Cell* cell, + const std::string& port_name) { RTLIL::Wire* sink_wire = NULL; if (!cell) { return sink_wire; @@ -154,7 +161,8 @@ if (selected_wires.size() > 0) { sink_wire = selected_wires.at(0); #ifdef SDC_DEBUG - log("Found sink wire: %s\n", RTLIL::unescape_id(sink_wire->name).c_str()); + log("Found sink wire: %s\n", + RTLIL::unescape_id(sink_wire->name).c_str()); #endif } return sink_wire;
diff --git a/sdc-plugin/sdc.cc b/sdc-plugin/sdc.cc index 60a1f83..d158e5b 100644 --- a/sdc-plugin/sdc.cc +++ b/sdc-plugin/sdc.cc
@@ -146,7 +146,8 @@ for (auto wire : module->wires()) { if (design->selected(module, wire)) { #ifdef SDC_DEBUG - log("Selected wire %s\n", RTLIL::unescape_id(wire->name).c_str()); + log("Selected wire %s\n", + RTLIL::unescape_id(wire->name).c_str()); #endif selected_wires.push_back(wire); } @@ -159,7 +160,7 @@ name = RTLIL::unescape_id(selected_wires.at(0)->name); } clocks_.AddClock(name, selected_wires, period, rising_edge, - falling_edge); + falling_edge); log("Created clock %s with period %f, waveform {%f %f}\n", name.c_str(), period, rising_edge, falling_edge); } @@ -225,8 +226,10 @@ std::array<std::unique_ptr<Propagation>, 3> passes{ std::unique_ptr<NaturalPropagation>( new NaturalPropagation(design, this)), - std::unique_ptr<BufferPropagation>(new BufferPropagation(design, this)), - std::unique_ptr<ClockDividerPropagation>(new ClockDividerPropagation(design, this))}; + std::unique_ptr<BufferPropagation>( + new BufferPropagation(design, this)), + std::unique_ptr<ClockDividerPropagation>( + new ClockDividerPropagation(design, this))}; for (auto& pass : passes) { pass->Run(clocks_); @@ -240,7 +243,7 @@ public: SdcPlugin() : write_sdc_cmd_(clocks_), - create_clock_cmd_(clocks_), + create_clock_cmd_(clocks_), get_clocks_cmd_(clocks_), propagate_clocks_cmd_(clocks_) { log("Loaded SDC plugin\n");