systemverilog-plugin/tests/break_continue/break_continue.v

// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//     http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top(output int a, output int b);
   initial begin
      a = 0;
      b = 0;
      repeat(15) begin
         if(a > 100) begin
            if (b > 10)
               break;
            b = b + 5;
            continue;
         end
         a = a + 10;
      end
   end
endmodule