ql-qlf: qlf_k6n10f: add clkbuf_sink attribute to clocks Signed-off-by: Paweł Czarnecki <pczarnecki@antmicro.com>

diff --git a/ql-qlf-plugin/qlf_k6n10f/TDP18Kx18_FIFO.v b/ql-qlf-plugin/qlf_k6n10f/TDP18Kx18_FIFO.v
index 185cb96..e45a4aa 100644
--- a/ql-qlf-plugin/qlf_k6n10f/TDP18Kx18_FIFO.v
+++ b/ql-qlf-plugin/qlf_k6n10f/TDP18Kx18_FIFO.v

@@ -59,7 +59,9 @@
 	input wire WEN_B;
 	input wire REN_A;
 	input wire REN_B;
+	(* clkbuf_sink *)
 	input wire CLK_A;
+	(* clkbuf_sink *)
 	input wire CLK_B;
 	input wire [1:0] BE_A;
 	input wire [1:0] BE_B;

diff --git a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
index 9ea74c4..181d7f2 100644
--- a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
+++ b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v

@@ -561,7 +561,9 @@
 	input wire WEN_B1;
 	input wire REN_A1;
 	input wire REN_B1;
+	(* clkbuf_sink *)
 	input wire CLK_A1;
+	(* clkbuf_sink *)
 	input wire CLK_B1;
 	input wire [1:0] BE_A1;
 	input wire [1:0] BE_B1;
@@ -587,7 +589,9 @@
 	input wire WEN_B2;
 	input wire REN_A2;
 	input wire REN_B2;
+	(* clkbuf_sink *)
 	input wire CLK_A2;
+	(* clkbuf_sink *)
 	input wire CLK_B2;
 	input wire [1:0] BE_A2;
 	input wire [1:0] BE_B2;

diff --git a/ql-qlf-plugin/qlf_k6n10f/sram1024x18.v b/ql-qlf-plugin/qlf_k6n10f/sram1024x18.v
index 79e5ae7..3974761 100644
--- a/ql-qlf-plugin/qlf_k6n10f/sram1024x18.v
+++ b/ql-qlf-plugin/qlf_k6n10f/sram1024x18.v

@@ -22,6 +22,7 @@
 	wdata_b,
 	rdata_b
 );
+	(* clkbuf_sink *)
 	input wire clk_a;
 	input wire cen_a;
 	input wire wen_a;
@@ -29,6 +30,7 @@
 	input wire [17:0] wmsk_a;
 	input wire [17:0] wdata_a;
 	output reg [17:0] rdata_a;
+	(* clkbuf_sink *)
 	input wire clk_b;
 	input wire cen_b;
 	input wire wen_b;

diff --git a/ql-qlf-plugin/qlf_k6n10f/ufifo_ctl.v b/ql-qlf-plugin/qlf_k6n10f/ufifo_ctl.v
index ad26b22..e1fb11c 100644
--- a/ql-qlf-plugin/qlf_k6n10f/ufifo_ctl.v
+++ b/ql-qlf-plugin/qlf_k6n10f/ufifo_ctl.v

@@ -34,8 +34,10 @@
 	input wire [2:0] depth;
 	input wire [1:0] rmode;
 	input wire [1:0] wmode;
+	(* clkbuf_sink *)
 	input wire rclk;
 	input wire rst_R_n;
+	(* clkbuf_sink *)
 	input wire wclk;
 	input wire rst_W_n;
 	input wire ren;