Removed emission of dff/dffn and latch/latchn. Replaced those with sdffsre/sdffnsre and latchsre/latchnsre respectively. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
diff --git a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v index 5da2aae..feeb46b 100644 --- a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v +++ b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
@@ -126,34 +126,6 @@ (* abc9_flop, lib_whitebox *) -module dff( - output reg Q, - input wire D, - (* clkbuf_sink *) - input wire C -); - initial Q <= 1'b0; - - always @(posedge C) - Q <= D; - -endmodule - -(* abc9_flop, lib_whitebox *) -module dffn( - output reg Q, - input wire D, - (* clkbuf_sink *) - input wire C -); - initial Q <= 1'b0; - - always @(negedge C) - Q <= D; - -endmodule - -(* abc9_flop, lib_whitebox *) module dffsre( output reg Q, input wire D, @@ -242,32 +214,6 @@ endmodule (* abc9_flop, lib_whitebox *) -module latch ( - output reg Q, - input wire D, - input wire G -); - initial Q <= 1'b0; - - always @(G) - if (G) Q <= D; - -endmodule - -(* abc9_flop, lib_whitebox *) -module latchn ( - output reg Q, - input wire D, - input wire G -); - initial Q <= 1'b0; - - always @(G) - if (!G) Q <= D; - -endmodule - -(* abc9_flop, lib_whitebox *) module latchsre ( output reg Q, input wire S,
diff --git a/ql-qlf-plugin/qlf_k6n10f/ffs_map.v b/ql-qlf-plugin/qlf_k6n10f/ffs_map.v index c510457..26fa6ed 100644 --- a/ql-qlf-plugin/qlf_k6n10f/ffs_map.v +++ b/ql-qlf-plugin/qlf_k6n10f/ffs_map.v
@@ -14,21 +14,6 @@ // // SPDX-License-Identifier: Apache-2.0 -// DFF, no set/reset, no enable -module \$_DFF_P_ (D, C, Q); - input D; - input C; - output Q; - dff _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q)); -endmodule - -module \$_DFF_N_ (D, C, Q); - input D; - input C; - output Q; - dffn _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q)); -endmodule - // DFF, asynchronous set/reset, enable module \$_DFFSRE_PNNP_ (C, S, R, E, D, Q); input C; @@ -89,11 +74,11 @@ // Latch, no set/reset, no enable module \$_DLATCH_P_ (input E, D, output Q); - latch _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E)); + latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(1'b1), .S(1'b1)); endmodule module \$_DLATCH_N_ (input E, D, output Q); - latchn _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E)); + latchnsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(1'b1), .S(1'b1)); endmodule // Latch with async set and reset and enable
diff --git a/ql-qlf-plugin/synth_quicklogic.cc b/ql-qlf-plugin/synth_quicklogic.cc index 4c9e6fc..16dd36c 100644 --- a/ql-qlf-plugin/synth_quicklogic.cc +++ b/ql-qlf-plugin/synth_quicklogic.cc
@@ -363,7 +363,10 @@ // $_DLATCH_SRPPP_ 0"); } else if (family == "qlf_k6n10f") { run("shregmap -minlen 8 -maxlen 20"); - run("dfflegalize -cell $_DFF_?_ 0 -cell $_DFFSRE_?NNP_ 0 -cell $_SDFFE_?N?P_ 0 -cell $_DLATCH_?_ 0 -cell $_DLATCHSR_?NN_ 0"); + // FIXME: dfflegalize seems to leave $_DLATCH_[NP]_ even if it + // is not allowed. So we allow them and map them later to + // $_DLATCHSR_[NP]NN_. + run("dfflegalize -cell $_DFFSRE_?NNP_ 0 -cell $_SDFFE_?N?P_ 0 -cell $_DLATCHSR_?NN_ 0 -cell $_DLATCH_?_ 0"); } else if (family == "pp3") { run("dfflegalize -cell $_DFFSRE_PPPP_ 0 -cell $_DLATCH_?_ x"); run("techmap -map +/quicklogic/" + family + "/cells_map.v");
diff --git a/ql-qlf-plugin/tests/dffs/dffs.tcl b/ql-qlf-plugin/tests/dffs/dffs.tcl index f589661..fd75277 100644 --- a/ql-qlf-plugin/tests/dffs/dffs.tcl +++ b/ql-qlf-plugin/tests/dffs/dffs.tcl
@@ -424,7 +424,7 @@ design -load postopt yosys cd my_dff stat -select -assert-count 1 t:dff +select -assert-count 1 t:sdffsre # DFFN design -load read @@ -434,7 +434,7 @@ design -load postopt yosys cd my_dffn stat -select -assert-count 1 t:dffn +select -assert-count 1 t:sdffnsre # DFFSRE from DFFR_N @@ -617,7 +617,7 @@ design -load postopt yosys cd my_latch stat -select -assert-count 1 t:latch +select -assert-count 1 t:latchsre # LATCHN design -load read @@ -627,7 +627,7 @@ design -load postopt yosys cd my_latchn stat -select -assert-count 1 t:latchn +select -assert-count 1 t:latchnsre ## LATCHSRE from LATCHR_N