commit 19cf6f6cef232453da7bce796bf3b85afa5b0da4
author Tomasz Michalak <tmichalak@antmicro.com> Mon Aug 17 13:34:03 2020 +0200
committer Tomasz Michalak <tmichalak@antmicro.com> Fri Sep 11 14:28:05 2020 +0200
tree 75d13d8179205fc3927803c67f1bd2a98bf54b99
parent 5b41747f738faeb300d880349f863e965fff6691

SDC: Don't add new line between wires

Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>

sdc-plugin/clocks.cc

diff --git a/sdc-plugin/clocks.cc b/sdc-plugin/clocks.cc
index a9b4607..d7056c1 100644
--- a/sdc-plugin/clocks.cc
+++ b/sdc-plugin/clocks.cc
@@ -168,8 +168,9 @@
 	}
 	file << " -waveform {" << clock.RisingEdge() << " " << clock.FallingEdge() << "}";
 	for (auto clock_wire : clock_wires) {
-	   file << " " << RTLIL::unescape_id(clock_wire->name) << std::endl;
+	   file << " " << RTLIL::unescape_id(clock_wire->name);
 	}
+	file << std::endl;
     }
 }