SDC: Don't add new line between wires

Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>

sdc-plugin/clocks.cc

diff --git a/sdc-plugin/clocks.cc b/sdc-plugin/clocks.cc
index a9b4607..d7056c1 100644
--- a/sdc-plugin/clocks.cc
+++ b/sdc-plugin/clocks.cc
@@ -168,8 +168,9 @@
 	}
 	file << " -waveform {" << clock.RisingEdge() << " " << clock.FallingEdge() << "}";
 	for (auto clock_wire : clock_wires) {
-	   file << " " << RTLIL::unescape_id(clock_wire->name) << std::endl;
+	   file << " " << RTLIL::unescape_id(clock_wire->name);
 	}
+	file << std::endl;
     }
 }