Fixed the ql-iob plugin to work with multi-bit nets Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
diff --git a/ql-iob-plugin/ql-iob.cc b/ql-iob-plugin/ql-iob.cc index e382cea..47d04a9 100644 --- a/ql-iob-plugin/ql-iob.cc +++ b/ql-iob-plugin/ql-iob.cc
@@ -27,6 +27,10 @@ #include <regex> #include <sstream> +#ifndef YOSYS_OVERRIDE +#define YOSYS_OVERRIDE override +#endif + USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -213,32 +217,42 @@ auto sigspec = cell->connections().at(port); // Get the connected wire - // FIXME: This assumes that the cell is directly connected to a - // top-level port. - if (sigspec.is_wire()) { - auto wire = sigspec.as_wire(); + for (auto sigbit : sigspec.bits()) { + if (sigbit.wire != nullptr) { + auto wire = sigbit.wire; - // Has to be top level wire - if (wire->port_input || wire->port_output) { + // Has to be top level wire + if (wire->port_input || wire->port_output) { - // Check if the wire is constrained - netName = RTLIL::unescape_id(wire->name); - if (constraintMap.count(netName)) { + // Check if the wire is constrained. Get pad name. + std::string baseName = RTLIL::unescape_id(wire->name); + std::string netNames[] = { + baseName, + stringf("%s[%d]", baseName.c_str(), sigbit.offset), + stringf("%s(%d)", baseName.c_str(), sigbit.offset), + }; - // Get the constraint - auto constraint = constraintMap.at(netName); + padName = ""; + netName = ""; + + for (auto& name : netNames) { + if (constraintMap.count(name)) { + auto constraint = constraintMap.at(name); + padName = constraint.padName; + netName = name; + break; + } + } // Check if there is an entry in the pinmap for this pad name - if (pinmapMap.count(constraint.padName)) { + if (pinmapMap.count(padName)) { // Choose a correct entry for the cell auto entry = choosePinmapEntry( - pinmapMap.at(constraint.padName), + pinmapMap.at(padName), ioCellType ); - padName = constraint.padName; - // Location string if (entry.count("x") && entry.count("y")) { locName = stringf("X%sY%s",