Updated nexus DSP rules, added test for a complex DSP block Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
diff --git a/dsp-ff-plugin/nexus-dsp_rules.txt b/dsp-ff-plugin/nexus-dsp_rules.txt index 7d35b84..9093182 100644 --- a/dsp-ff-plugin/nexus-dsp_rules.txt +++ b/dsp-ff-plugin/nexus-dsp_rules.txt
@@ -68,91 +68,88 @@ endport enddsp -# TODO: Uncomment when support for multiple port registers controlled by -# a common parameter is added: +dsp MULTADDSUB9X9WIDE + port A0 + clk CLK 0 + rst RSTA0A1 0 + ena CEA0A1 1 -#dsp MULTADDSUB9X9WIDE -# port A0 -# clk CLK 0 -# rst RSTA0A1 0 -# ena CEA0A1 1 -# -# set REGINPUTAB0=REGISTER -# map GSR=GSR -# endport -# port A1 -# clk CLK 0 -# rst RSTA0A1 0 -# ena CEA0A1 1 -# -# set REGINPUTAB1=REGISTER -# map GSR=GSR -# endport -# port A2 -# clk CLK 0 -# rst RSTA2A3 0 -# ena CEA2A3 1 -# -# set REGINPUTAB2=REGISTER -# map GSR=GSR -# endport -# port A3 -# clk CLK 0 -# rst RSTA2A3 0 -# ena CEA2A3 1 -# -# set REGINPUTAB3=REGISTER -# map GSR=GSR -# endport -# port B0 -# clk CLK 0 -# rst RSTB0B1 0 -# ena CEB0B1 1 -# -# set REGINPUTAB0=REGISTER -# map GSR=GSR -# endport -# port B1 -# clk CLK 0 -# rst RSTB0B1 0 -# ena CEB0B1 1 -# -# set REGINPUTAB1=REGISTER -# map GSR=GSR -# endport -# port B2 -# clk CLK 0 -# rst RSTB2B3 0 -# ena CEB2B3 1 -# -# set REGINPUTAB2=REGISTER -# map GSR=GSR -# endport -# port B3 -# clk CLK 0 -# rst RSTB2B3 0 -# ena CEB2B3 1 -# -# set REGINPUTAB3=REGISTER -# map GSR=GSR -# endport -# port C -# clk CLK 0 -# rst RSTC0 -# ena CEC 1 -# -# set REGINPUTC=REGISTER -# map GSR=GSR -# endport -# port Z -# clk CLK 0 -# rst RSTOUT 0 -# ena CEOUT 1 -# -# set REGOUTPUT=REGISTER -# map GSR=GSR -# endport -#enddsp + set REGINPUTAB0=REGISTER + map GSR=GSR + endport + port A1 + clk CLK 0 + rst RSTA0A1 0 + ena CEA0A1 1 + + set REGINPUTAB1=REGISTER + map GSR=GSR + endport + port A2 + clk CLK 0 + rst RSTA2A3 0 + ena CEA2A3 1 + + set REGINPUTAB2=REGISTER + map GSR=GSR + endport + port A3 + clk CLK 0 + rst RSTA2A3 0 + ena CEA2A3 1 + + set REGINPUTAB3=REGISTER + map GSR=GSR + endport + port B0 + clk CLK 0 + rst RSTB0B1 0 + ena CEB0B1 1 + + set REGINPUTAB0=REGISTER + map GSR=GSR + endport + port B1 + clk CLK 0 + rst RSTB0B1 0 + ena CEB0B1 1 + + set REGINPUTAB1=REGISTER + map GSR=GSR + endport + port B2 + clk CLK 0 + rst RSTB2B3 0 + ena CEB2B3 1 + + set REGINPUTAB2=REGISTER + map GSR=GSR + endport + port B3 + clk CLK 0 + rst RSTB2B3 0 + ena CEB2B3 1 + + set REGINPUTAB3=REGISTER + map GSR=GSR + endport + port C + clk CLK 0 + rst RSTC 0 + ena CEC 1 + + set REGINPUTC=REGISTER + map GSR=GSR + endport + port Z + clk CLK 0 + rst RSTOUT 0 + ena CEOUT 1 + + set REGOUTPUT=REGISTER + map GSR=GSR + endport +enddsp ff FD1P3DX clk CK
diff --git a/dsp-ff-plugin/tests/Makefile b/dsp-ff-plugin/tests/Makefile index d559175..305092f 100644 --- a/dsp-ff-plugin/tests/Makefile +++ b/dsp-ff-plugin/tests/Makefile
@@ -8,6 +8,7 @@ TESTS = \ nexus_mult \ + nexus_mult_wide \ nexus_fftypes \ nexus_conn_conflict \ nexus_conn_share \ @@ -16,6 +17,7 @@ include $(shell pwd)/../../Makefile_test.common nexus_mult_verify = true +nexus_mult_wide_verify = true nexus_fftypes_verify = true nexus_conn_conflict_verify = true nexus_conn_share_verify = true
diff --git a/dsp-ff-plugin/tests/nexus_mult_wide/nexus_mult_wide.tcl b/dsp-ff-plugin/tests/nexus_mult_wide/nexus_mult_wide.tcl new file mode 100644 index 0000000..70f5a61 --- /dev/null +++ b/dsp-ff-plugin/tests/nexus_mult_wide/nexus_mult_wide.tcl
@@ -0,0 +1,18 @@ +yosys -import +if { [info procs dsp_ff] == {} } { plugin -i dsp-ff } +yosys -import ;# ingest plugin commands + +read_verilog $::env(DESIGN_TOP).v +design -save read + +set TOP "mult_wide" +design -load read +hierarchy -top ${TOP} +synth_nexus -flatten +techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO +equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ../../nexus-dsp_rules.txt +design -load postopt +yosys cd ${TOP} +stat +select -assert-count 1 t:MULTADDSUB9X9WIDE +select -assert-count 9 t:FD1P3IX
diff --git a/dsp-ff-plugin/tests/nexus_mult_wide/nexus_mult_wide.v b/dsp-ff-plugin/tests/nexus_mult_wide/nexus_mult_wide.v new file mode 100644 index 0000000..cb539e5 --- /dev/null +++ b/dsp-ff-plugin/tests/nexus_mult_wide/nexus_mult_wide.v
@@ -0,0 +1,63 @@ +// Copyright (C) 2020-2021 The SymbiFlow Authors. +// +// Use of this source code is governed by a ISC-style +// license that can be found in the LICENSE file or at +// https://opensource.org/licenses/ISC +// +// SPDX-License-Identifier:ISC + +module mult_wide ( + input wire CLK, + input wire [ 8:0] A0, + input wire [ 8:0] A1, + input wire [ 8:0] A2, + input wire [ 8:0] A3, + input wire [ 8:0] B0, + input wire [ 8:0] B1, + input wire [ 8:0] B2, + input wire [ 8:0] B3, + input wire [53:0] C, + output wire [53:0] Z +); + + reg [8:0] ra0; + always @(posedge CLK) + ra0 <= A0; + + reg [8:0] rb0; + always @(posedge CLK) + rb0 <= B0; + + reg [8:0] rb2; + always @(posedge CLK) + rb2 <= B2; + + MULTADDSUB9X9WIDE # ( + .REGINPUTAB0("BYPASS"), + .REGINPUTAB1("BYPASS"), + .REGINPUTAB2("BYPASS"), + .REGINPUTAB3("BYPASS"), + .REGINPUTC("BYPASS"), + .REGADDSUB("BYPASS"), + .REGLOADC("BYPASS"), + .REGLOADC2("BYPASS"), + .REGPIPELINE("BYPASS"), + .REGOUTPUT("REGISTER") + ) mult ( + .A0 (ra0), + .A1 (A1), + .A2 (A2), + .A3 (A3), + .B0 (rb0), + .B1 (B1), + .B2 (rb2), + .B3 (B3), + .C (C), + .Z (Z), + + .LOADC (1'b0), + .ADDSUB (4'hF), + .SIGNED (1'b1), + ); + +endmodule
diff --git a/dsp-ff-plugin/tests/nexus_param_conflict/nexus_param_conflict.tcl b/dsp-ff-plugin/tests/nexus_param_conflict/nexus_param_conflict.tcl index abd9d3c..ff46e0b 100644 --- a/dsp-ff-plugin/tests/nexus_param_conflict/nexus_param_conflict.tcl +++ b/dsp-ff-plugin/tests/nexus_param_conflict/nexus_param_conflict.tcl
@@ -25,7 +25,7 @@ yosys cd ${TOP} stat select -assert-count 1 t:MULT9X9 -select -assert-count 9 t:FD1P3IX t:DS1P3DX %u +select -assert-count 9 t:FD1P3IX t:FD1P3DX %u set TOP "conflict_ff_param" design -load read