SDC: Fix all propagation types to use attributes Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
diff --git a/sdc-plugin/clocks.cc b/sdc-plugin/clocks.cc index 3727ec6..3a856c3 100644 --- a/sdc-plugin/clocks.cc +++ b/sdc-plugin/clocks.cc
@@ -25,7 +25,7 @@ void Clocks::AddClock(const std::string& name, std::vector<RTLIL::Wire*> wires, float period, float rising_edge, float falling_edge) { - std::for_each(wires.begin(), wires.end(), [&, this](RTLIL::Wire* wire) { + std::for_each(wires.begin(), wires.end(), [&](RTLIL::Wire* wire) { AddClock(name, wire, period, rising_edge, falling_edge); }); } @@ -41,9 +41,9 @@ wire->set_string_attribute(RTLIL::escape_id("WAVEFORM"), waveform); } -void Clocks::AddClock(Clock& clock) { - AddClock(clock.Name(), clock.GetClockWires(), clock.Period(), - clock.RisingEdge(), clock.FallingEdge()); +void Clocks::AddClock(RTLIL::Wire* wire, float period, + float rising_edge, float falling_edge) { + AddClock(Clock::ClockWireName(wire), wire, period, rising_edge, falling_edge); } const std::vector<RTLIL::Wire*> Clocks::GetClocks(RTLIL::Design* design) { @@ -69,8 +69,9 @@ log("Processing clock %s\n", RTLIL::id2cstr(clock_wire->name)); #endif auto aliases = pass->FindAliasWires(clock_wire); - /* AddClock(clock.Name(), aliases, clock.Period(), */ - /* clock.RisingEdge(), clock.FallingEdge()); */ + AddClock(Clock::ClockWireName(clock_wire), aliases, + Clock::Period(clock_wire), Clock::RisingEdge(clock_wire), + Clock::FallingEdge(clock_wire)); } #ifdef SDC_DEBUG log("Finish natural clock propagation\n\n"); @@ -82,25 +83,11 @@ log("Start buffer clock propagation\n"); log("IBUF pass\n"); #endif - for (auto& clock_wire : Clocks::GetClocks(design)) { -#ifdef SDC_DEBUG - log("Processing clock %s\n", RTLIL::id2cstr(clock_wire->name)); -#endif - auto period = std::stof(clock_wire->get_string_attribute(RTLIL::escape_id("PERIOD"))); - auto clock = Clock(clock_wire, period, 0, period/2); - PropagateThroughBuffer(pass, design, clock, IBuf()); - } + PropagateThroughBuffers(pass, design, IBuf()); #ifdef SDC_DEBUG log("BUFG pass\n"); #endif - for (auto& clock_wire : Clocks::GetClocks(design)) { -#ifdef SDC_DEBUG - log("Processing clock %s\n", RTLIL::id2cstr(clock_wire->name)); -#endif - auto period = std::stof(clock_wire->get_string_attribute(RTLIL::escape_id("PERIOD"))); - auto clock = Clock(clock_wire, period, 0, period/2); - PropagateThroughBuffer(pass, design, clock, Bufg()); - } + PropagateThroughBuffers(pass, design, Bufg()); #ifdef SDC_DEBUG log("Finish buffer clock propagation\n\n"); #endif @@ -114,28 +101,19 @@ #ifdef SDC_DEBUG log("Processing clock %s\n", RTLIL::id2cstr(clock_wire->name)); #endif - auto period = std::stof(clock_wire->get_string_attribute(RTLIL::escape_id("PERIOD"))); - auto clock = Clock(clock_wire, period, 0, period/2); - auto pll_clocks = - pass->FindSinkClocksForCellType(clock, "PLLE2_ADV"); - for (auto pll_clock : pll_clocks) { -#ifdef SDC_DEBUG - log("PLL clock: %s\n", pll_clock.Name().c_str()); -#endif - AddClock(pll_clock); - PropagateThroughBuffer(pass, design, pll_clock, Bufg()); - } + pass->PropagateClocksForCellType(clock_wire, "PLLE2_ADV"); + PropagateThroughBuffers(pass, design, Bufg()); } #ifdef SDC_DEBUG log("Finish clock divider clock propagation\n\n"); #endif } -void Clocks::PropagateThroughBuffer(Propagation* pass, RTLIL::Design* design, Clock& clock, +void Clocks::PropagateThroughBuffers(Propagation* pass, RTLIL::Design* design, Buffer buffer) { for (auto& clock_wire : Clocks::GetClocks(design)) { #ifdef SDC_DEBUG - log("Clock wire %s\n", RTLIL::id2cstr(clock_wire->name)); + log("Clock wire %s\n", Clock::ClockWireName(clock_wire).c_str()); #endif auto buf_wires = pass->FindSinkWiresForCellType(clock_wire, buffer.name, buffer.output); @@ -146,9 +124,9 @@ RTLIL::id2cstr(wire->name)); #endif path_delay += buffer.delay; - AddClock(RTLIL::unescape_id(wire->name), wire, clock.Period(), - clock.RisingEdge() + path_delay, - clock.FallingEdge() + path_delay); + AddClock(wire, Clock::Period(clock_wire), + Clock::RisingEdge(clock_wire) + path_delay, + Clock::FallingEdge(clock_wire) + path_delay); } } }
diff --git a/sdc-plugin/clocks.h b/sdc-plugin/clocks.h index 478b9ea..9a74b4a 100644 --- a/sdc-plugin/clocks.h +++ b/sdc-plugin/clocks.h
@@ -39,7 +39,6 @@ float rising_edge, float falling_edge); std::vector<RTLIL::Wire*> GetClockWires() { return clock_wires_; } const std::string& Name() const { return name_; } - float Period() { return period_; } static float Period(RTLIL::Wire* clock_wire); float RisingEdge() { return rising_edge_; } static float RisingEdge(RTLIL::Wire* clock_wire); @@ -66,18 +65,19 @@ class Clocks { public: - void AddClock(const std::string& name, std::vector<RTLIL::Wire*> wires, + static void AddClock(const std::string& name, std::vector<RTLIL::Wire*> wires, float period, float rising_edge, float falling_edge); - void AddClock(const std::string& name, RTLIL::Wire* wire, float period, + static void AddClock(const std::string& name, RTLIL::Wire* wire, float period, float rising_edge, float falling_edge); - void AddClock(Clock& clock); + static void AddClock(RTLIL::Wire* wire, float period, + float rising_edge, float falling_edge); + static const std::vector<RTLIL::Wire*> GetClocks(RTLIL::Design* design); void Propagate(RTLIL::Design* design, NaturalPropagation* pass); void Propagate(RTLIL::Design* design, BufferPropagation* pass); void Propagate(RTLIL::Design* design, ClockDividerPropagation* pass); - static const std::vector<RTLIL::Wire*> GetClocks(RTLIL::Design* design); private: - void PropagateThroughBuffer(Propagation* pass, RTLIL::Design* design, Clock& clock, + void PropagateThroughBuffers(Propagation* pass, RTLIL::Design* design, Buffer buffer); };
diff --git a/sdc-plugin/propagation.cc b/sdc-plugin/propagation.cc index 3ea35ad..71ce467 100644 --- a/sdc-plugin/propagation.cc +++ b/sdc-plugin/propagation.cc
@@ -37,34 +37,30 @@ return alias_wires; } -std::vector<Clock> ClockDividerPropagation::FindSinkClocksForCellType( - Clock driving_clock, const std::string& cell_type) { - std::vector<Clock> clocks; - auto clock_wire = driving_clock.ClockWire(); +void ClockDividerPropagation::PropagateClocksForCellType( + RTLIL::Wire* driver_wire, const std::string& cell_type) { if (cell_type == "PLLE2_ADV") { RTLIL::Cell* cell = NULL; for (auto input : Pll::inputs) { - cell = FindSinkCellOnPort(clock_wire, input); + cell = FindSinkCellOnPort(driver_wire, input); if (cell and RTLIL::unescape_id(cell->type) == cell_type) { break; } } if (!cell) { - return clocks; + return; } - Pll pll(cell, driving_clock.Period(), driving_clock.RisingEdge()); + Pll pll(cell, Clock::Period(driver_wire), Clock::RisingEdge(driver_wire)); for (auto output : Pll::outputs) { RTLIL::Wire* wire = FindSinkWireOnPort(cell, output); if (wire) { float clkout_period(pll.clkout_period.at(output)); float clkout_rising_edge(pll.clkout_rising_edge.at(output)); float clkout_falling_edge(pll.clkout_falling_edge.at(output)); - Clock clock(wire, clkout_period, clkout_rising_edge, clkout_falling_edge); - clocks.push_back(clock); + Clocks::AddClock(wire, clkout_period, clkout_rising_edge, clkout_falling_edge); } } } - return clocks; } RTLIL::Cell* Propagation::FindSinkCellOfType(RTLIL::Wire* wire,
diff --git a/sdc-plugin/propagation.h b/sdc-plugin/propagation.h index 0e45211..f9f06ac 100644 --- a/sdc-plugin/propagation.h +++ b/sdc-plugin/propagation.h
@@ -66,7 +66,7 @@ : Propagation(design, pass) {} void Run(Clocks& clocks) override { clocks.Propagate(design_, this); } - std::vector<Clock> FindSinkClocksForCellType(Clock driver_wire, + void PropagateClocksForCellType(RTLIL::Wire* driver_wire, const std::string& cell_type); }; #endif // PROPAGATION_H_
diff --git a/sdc-plugin/sdc.cc b/sdc-plugin/sdc.cc index b66a287..9d55906 100644 --- a/sdc-plugin/sdc.cc +++ b/sdc-plugin/sdc.cc
@@ -235,9 +235,9 @@ } std::array<std::unique_ptr<Propagation>, 2> passes{ - std::unique_ptr<BufferPropagation>( + std::unique_ptr<Propagation>( new BufferPropagation(design, this)), - std::unique_ptr<ClockDividerPropagation>( + std::unique_ptr<Propagation>( new ClockDividerPropagation(design, this))}; log("Perform clock propagation\n");