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foss-fpga-tools/yosys-symbiflow-plugins/2d260ec82a15ad464828ccf96c149ab61d5d9e54^!/.
commit
2d260ec82a15ad464828ccf96c149ab61d5d9e54
[log]
author
rakeshm <rakeshm@quicklogic.com>
Thu Dec 29 06:02:36 2022 -0800
committer
rakeshm <rakeshm@quicklogic.com>
Thu Dec 29 06:02:36 2022 -0800
tree
0f928c83951bcb4e9abe7a4d756975666a4131fd
parent
b28c0811c8d17b1d232c538d9cff004dcbdc67f4 [diff]
removed commented code, fixed indentation & code formatting issues

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram18k_sdp/sim/Makefile b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram18k_sdp/sim/Makefile
index ad94052..0cce75d 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram18k_sdp/sim/Makefile
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram18k_sdp/sim/Makefile

@@ -39,7 +39,6 @@
 	@rm -rf  $(word $(1),$(POST_SYNTH)).vcd $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).vvp.log $(word $(1),$(POST_SYNTH)).vcd.log
 endef
 
-#FIXME: $(call simulate_post_synth,3)
 sim:
 	$(call simulate_post_synth,1)
 	$(call clean_post_synth_sim,1)

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram18k_sdp/sim/asymmetric_bram18k_sdp_tb.v b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram18k_sdp/sim/asymmetric_bram18k_sdp_tb.v
index f71ee13..e8ffaa5 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram18k_sdp/sim/asymmetric_bram18k_sdp_tb.v
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram18k_sdp/sim/asymmetric_bram18k_sdp_tb.v

@@ -4,7 +4,7 @@
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
 //
-//     http://www.apache.org/licenses/LICENSE-2.0
+//		 http://www.apache.org/licenses/LICENSE-2.0
 //
 // Unless required by applicable law or agreed to in writing, software
 // distributed under the License is distributed on an "AS IS" BASIS,
@@ -23,7 +23,7 @@
 	localparam ADDR_INCR = 1;
 
 	reg clk_0;
-  reg clk_1;
+	reg clk_1;
 	reg rce;
 	reg [`ADDR_WIDTH1-1:0] ra;
 	wire [`DATA_WIDTH1-1:0] rq;
@@ -34,12 +34,11 @@
 	initial clk_0 = 0;
 	initial clk_1 = 0;
 	initial ra = 0;
-  initial wa = 0;
-  initial wd = 0;
+	initial wa = 0;
+	initial wd = 0;
 	initial rce = 0;
-  initial wce = 0;
+	initial wce = 0;
 	initial forever #(PERIOD / 2.0) clk_0 = ~clk_0;
-  //initial forever #(PERIOD / 2.0) clk_1 = ~clk_1;
 	initial begin
 		#(PERIOD / 4.0);
 		forever #(PERIOD / 2.0) clk_1 = ~clk_1;
@@ -72,76 +71,76 @@
 			error_0_cnt <= error_0_cnt + 1'b1;
 	end
 
-case (`STRINGIFY(`TOP))
-"spram_9x2048_18x1024": begin
-	initial #(1) begin
-		// Write data
-		for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
-			@(negedge clk_0) begin
-				wa = a[`ADDR_WIDTH0-1:0];
-				wd = a[9:1];
-				wce = 1;
-			end
-			@(posedge clk_0) begin
-				#(PERIOD/10) wce = 0;
-			end
-		end
-		// Read data
-		read_test_0 = 1;
-		for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
-			@(negedge clk_1) begin
-				ra = a;
-				rce = 1;
-			end
-			@(posedge clk_1) begin
-        expected_0 <= {a[8],a[8],a[7:0],a[7:0]};
-				#(PERIOD/10) rce = 0;
-				if ( rq !== expected_0) begin
-					$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, rq, expected_0, a);
-				end else begin
-					$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, rq, expected_0, a);
+	case (`STRINGIFY(`TOP))
+	"spram_9x2048_18x1024": begin
+		initial #(1) begin
+			// Write data
+			for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
+				@(negedge clk_0) begin
+					wa = a[`ADDR_WIDTH0-1:0];
+					wd = a[9:1];
+					wce = 1;
+				end
+				@(posedge clk_0) begin
+					#(PERIOD/10) wce = 0;
 				end
 			end
-		end
-		done_0 = 1'b1;
-    a = 0;
-	end
-end
-"spram_18x1024_9x2048": begin
-	initial #(1) begin
-		// Write data
-		for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
-			@(negedge clk_0) begin
-				wa = a[`ADDR_WIDTH0-1:0];
-				wd = {a[8],a[8],a[7:0],a[7:0]};
-				wce = 1;
-			end
-			@(posedge clk_0) begin
-				#(PERIOD/10) wce = 0;
-			end
-		end
-		// Read data
-		read_test_0 = 1;
-		for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
-			@(negedge clk_1) begin
-				ra = a;
-				rce = 1;
-			end
-			@(posedge clk_1) begin
-        expected_0 <= {a[9:1]};
-				#(PERIOD/10) rce = 0;
-				if ( rq !== expected_0) begin
-					$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, rq, expected_0, a);
-				end else begin
-					$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, rq, expected_0, a);
+			// Read data
+			read_test_0 = 1;
+			for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
+				@(negedge clk_1) begin
+					ra = a;
+					rce = 1;
+				end
+				@(posedge clk_1) begin
+					expected_0 <= {a[8],a[8],a[7:0],a[7:0]};				
+					#(PERIOD/10) rce = 0;
+					if ( rq !== expected_0) begin
+						$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, rq, expected_0, a);
+					end else begin
+						$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, rq, expected_0, a);
+					end
 				end
 			end
+			done_0 = 1'b1;
+			a = 0;		
 		end
-		done_0 = 1'b1;
-    a = 0;
 	end
-end  
-endcase
+	"spram_18x1024_9x2048": begin
+		initial #(1) begin
+			// Write data
+			for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
+				@(negedge clk_0) begin
+					wa = a[`ADDR_WIDTH0-1:0];
+					wd = {a[8],a[8],a[7:0],a[7:0]};
+					wce = 1;
+				end
+				@(posedge clk_0) begin
+					#(PERIOD/10) wce = 0;
+				end
+			end
+			// Read data
+			read_test_0 = 1;
+			for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
+				@(negedge clk_1) begin
+					ra = a;
+					rce = 1;
+				end
+				@(posedge clk_1) begin				
+					expected_0 <= {a[9:1]};
+					#(PERIOD/10) rce = 0;
+					if ( rq !== expected_0) begin
+						$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, rq, expected_0, a);
+					end else begin
+						$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, rq, expected_0, a);
+					end
+				end
+			end
+			done_0 = 1'b1;
+			a = 0;		
+		end
+	end	 
+	endcase
 
 	// Scan for simulation finish
 	always @(posedge clk_1) begin
@@ -153,7 +152,7 @@
 		"spram_9x2048_18x1024": begin
 			spram_9x2048_18x1024 #() bram (
 				.clock0(clk_0),
-        .clock1(clk_1),        
+				.clock1(clk_1),			
 				.REN_i(rce),
 				.RD_ADDR_i(ra),
 				.RDATA_o(rq),
@@ -165,7 +164,7 @@
 		"spram_18x1024_9x2048": begin
 			spram_18x1024_9x2048 #() bram (
 				.clock0(clk_0),
-        .clock1(clk_1),        
+				.clock1(clk_1),			
 				.REN_i(rce),
 				.RD_ADDR_i(ra),
 				.RDATA_o(rq),

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_afifo/asymmetric_bram36k_afifo.v b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_afifo/asymmetric_bram36k_afifo.v
index 031a4bd..6cef5f5 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_afifo/asymmetric_bram36k_afifo.v
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_afifo/asymmetric_bram36k_afifo.v

@@ -33,7 +33,7 @@
 
 
 AFIFO_36K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
-        				 ) 
+                 )
   FIFO_INST    (
                 .DIN(DIN),
                 .PUSH(PUSH),
@@ -53,8 +53,7 @@
                 .Empty(Empty),
 
                 .DOUT(DOUT)
-         				);
-
+                );
 endmodule
 
 module af2048x18_1024x36 (DIN,PUSH,POP,clock0,clock1,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
@@ -75,7 +74,7 @@
 output Overrun_Error, Underrun_Error;
 
 AFIFO_36K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
-        				 ) 
+                  )
   FIFO_INST    (
                 .DIN(DIN),
                 .PUSH(PUSH),
@@ -95,8 +94,7 @@
                 .Empty(Empty),
 
                 .DOUT(DOUT)
-         				);
-
+                );
 endmodule
 
 module af2048x18_4098x9 (DIN,PUSH,POP,clock0,clock1,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
@@ -117,7 +115,7 @@
 output Overrun_Error, Underrun_Error;
 
 AFIFO_36K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
-        				 ) 
+                  )
   FIFO_INST    (
                 .DIN(DIN),
                 .PUSH(PUSH),
@@ -137,8 +135,7 @@
                 .Empty(Empty),
 
                 .DOUT(DOUT)
-         				);
-
+                );
 endmodule
 
 module af1024x36_4098x9 (DIN,PUSH,POP,clock0,clock1,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
@@ -159,7 +156,7 @@
 output Overrun_Error, Underrun_Error;
 
 AFIFO_36K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
-        				 ) 
+                  )
   FIFO_INST    (
                 .DIN(DIN),
                 .PUSH(PUSH),
@@ -179,6 +176,5 @@
                 .Empty(Empty),
 
                 .DOUT(DOUT)
-         				);
-
+                );
 endmodule
\ No newline at end of file

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_afifo/sim/Makefile b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_afifo/sim/Makefile
index 9686158..76bc1c7 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_afifo/sim/Makefile
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_afifo/sim/Makefile

@@ -39,7 +39,6 @@
 	@rm -rf  $(word $(1),$(POST_SYNTH)).vcd $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).vvp.log $(word $(1),$(POST_SYNTH)).vcd.log
 endef
 
-#FIXME: $(call simulate_post_synth,3)
 sim:
 	$(call simulate_post_synth,1)
 	$(call clean_post_synth_sim,1)

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_afifo/sim/asymmetric_bram36k_afifo_tb.v b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_afifo/sim/asymmetric_bram36k_afifo_tb.v
index 5be25e7..dd40a5a 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_afifo/sim/asymmetric_bram36k_afifo_tb.v
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_afifo/sim/asymmetric_bram36k_afifo_tb.v

@@ -4,7 +4,7 @@
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
 //
-//     http://www.apache.org/licenses/LICENSE-2.0
+//	http://www.apache.org/licenses/LICENSE-2.0
 //
 // Unless required by applicable law or agreed to in writing, software
 // distributed under the License is distributed on an "AS IS" BASIS,
@@ -23,32 +23,32 @@
 	localparam ADDR_INCR = 1;
 
 	reg clk0;
-  reg clk1;
-  reg flush;
+	reg clk1;
+	reg flush;
 	reg pop;
 	wire [`DATA_WIDTH1-1:0] dout;
 	reg push;
-	reg [`DATA_WIDTH0-1:0] din;
-  wire almost_full,almost_empty;
-  wire full, empty;
-  wire full_watermark, empty_watermark;
-  wire overrun_error, underrun_error;
+	reg [`DATA_WIDTH0-1:0] din;	 
+	wire almost_full,almost_empty;
+	wire full, empty;
+	wire full_watermark, empty_watermark;
+	wire overrun_error, underrun_error;
 
-  initial 
-  begin
-    clk0 = 0;
-    clk1 = 0;
-    pop = 0;
-    push = 0;
-    flush = 1;
-    din = 0;
-    #40
-    flush = 0;
-  end
-  
+	initial 
+	begin
+		clk0 = 0;
+		clk1 = 0;
+		pop = 0;
+		push = 0;
+		flush = 1;
+		din = 0;
+		#40
+		flush = 0;
+	end
+	
 	initial forever #(PERIOD / 3.0) clk0 = ~clk0;
-  initial forever #(PERIOD / 2.0) clk1 = ~clk1;
-  
+	initial forever #(PERIOD / 2.0) clk1 = ~clk1;
+	
 	initial begin
 		$dumpfile(`STRINGIFY(`VCD));
 		$dumpvars;
@@ -58,12 +58,12 @@
 
 	reg done;
 	initial done = 1'b0;
-  
-  reg read_test;
+	
+	reg read_test;
 	initial read_test = 0;
 
 	reg [`DATA_WIDTH1-1:0] expected;
-  initial expected = 0;
+	initial expected = 0;
 
 	wire error = (read_test) ? dout !== expected : 0;
 
@@ -74,136 +74,136 @@
 			error_cnt <= error_cnt + 1'b1; 
 	end
 
-case (`STRINGIFY(`TOP))
-"af4096x9_1024x36": begin
-	initial #(50) begin
-		// Write data
-		for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
-			@(negedge clk0) begin
-				din = a[10:2];
-				push = 1;
-			end
-			@(posedge clk0) begin
-				#(PERIOD/10) push = 0;
-			end
-		end
-		// Read data
-		read_test = 1;
-		for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
-			@(posedge clk1) begin
-        expected <= {a[8],a[8],a[7:0],a[7:0],a[8],a[8],a[7:0],a[7:0]};
-				#(PERIOD/10) pop = 0;
-				if ( dout !== expected) begin
-					$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, dout, expected, a);
-				end else begin
-					$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, dout, expected, a);
+	case (`STRINGIFY(`TOP))
+	"af4096x9_1024x36": begin
+		initial #(50) begin
+			// Write data
+			for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
+				@(negedge clk0) begin
+					din = a[10:2];
+					push = 1;
+				end
+				@(posedge clk0) begin
+					#(PERIOD/10) push = 0;
 				end
 			end
-      @(negedge clk1) begin
-				pop = 1;
+			// Read data
+			read_test = 1;
+			for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
+				@(posedge clk1) begin
+					expected <= {a[8],a[8],a[7:0],a[7:0],a[8],a[8],a[7:0],a[7:0]};
+					#(PERIOD/10) pop = 0;
+					if ( dout !== expected) begin
+						$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, dout, expected, a);
+					end else begin
+						$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, dout, expected, a);
+					end
+				end
+				@(negedge clk1) begin
+					pop = 1;
+				end
 			end
+			done = 1'b1;
+			a = 0;
 		end
-		done = 1'b1;
-    a = 0;
 	end
-end
-"af2048x18_1024x36": begin
-	initial #(50) begin
-		// Write data
-		for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
-			@(negedge clk0) begin
-				din = a[18:1];
-				push = 1;
-			end
-			@(posedge clk0) begin
-				#(PERIOD/10) push = 0;
-			end
-		end
-		// Read data
-		read_test = 1;
-		for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
-			@(posedge clk1) begin
-        expected <= {a[17:0],a[17:0]};
-				#(PERIOD/10) pop = 0;
-				if ( dout !== expected) begin
-					$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, dout, expected, a);
-				end else begin
-					$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, dout, expected, a);
+	"af2048x18_1024x36": begin
+		initial #(50) begin
+			// Write data
+			for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
+				@(negedge clk0) begin
+					din = a[18:1];
+					push = 1;
+				end
+				@(posedge clk0) begin
+					#(PERIOD/10) push = 0;
 				end
 			end
-      @(negedge clk1) begin
-				pop = 1;
+			// Read data
+			read_test = 1;
+			for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
+				@(posedge clk1) begin
+					expected <= {a[17:0],a[17:0]};
+					#(PERIOD/10) pop = 0;
+					if ( dout !== expected) begin
+						$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, dout, expected, a);
+					end else begin
+						$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, dout, expected, a);
+					end
+				end
+				@(negedge clk1) begin
+					pop = 1;
+				end
 			end
+			done = 1'b1;
+			a = 0;
 		end
-		done = 1'b1;
-    a = 0;
+	end	 
+	"af2048x18_4098x9": begin
+		initial #(50) begin
+			// Write data
+			for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
+				@(negedge clk0) begin
+					din = {a[8],a[8],a[7:0],a[7:0]};
+					push = 1;
+				end
+				@(posedge clk0) begin
+					#(PERIOD/10) push = 0;
+				end
+			end
+			// Read data
+			read_test = 1;
+			for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
+				@(posedge clk1) begin
+					expected <= {a[9:1]};
+					#(PERIOD/10) pop = 0;
+					if ( dout !== expected) begin
+						$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, dout, expected, a);
+					end else begin
+						$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, dout, expected, a);
+					end
+				end
+				@(negedge clk1) begin
+					pop = 1;
+				end
+			end
+			done = 1'b1;
+			a = 0;
+		end
 	end
-end  
-"af2048x18_4098x9": begin
-	initial #(50) begin
-		// Write data
-		for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
-			@(negedge clk0) begin
-				din = {a[8],a[8],a[7:0],a[7:0]};
-				push = 1;
-			end
-			@(posedge clk0) begin
-				#(PERIOD/10) push = 0;
-			end
-		end
-		// Read data
-		read_test = 1;
-		for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
-			@(posedge clk1) begin
-        expected <= {a[9:1]};
-				#(PERIOD/10) pop = 0;
-				if ( dout !== expected) begin
-					$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, dout, expected, a);
-				end else begin
-					$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, dout, expected, a);
+	"af1024x36_4098x9": begin
+		initial #(50) begin
+			// Write data
+			for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
+				@(negedge clk0) begin
+					din = {a[8],a[8],a[7:0],a[7:0],a[8],a[8],a[7:0],a[7:0]};
+					push = 1;
+				end
+				@(posedge clk0) begin
+					#(PERIOD/10) push = 0;
 				end
 			end
-      @(negedge clk1) begin
-				pop = 1;
+			// Read data
+			read_test = 1;
+			for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
+				@(posedge clk1) begin
+					expected <= {a[10:2]};
+					#(PERIOD/10) pop = 0;
+					if ( dout !== expected) begin
+						$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, dout, expected, a);
+					end else begin
+						$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, dout, expected, a);
+					end
+				end
+				@(negedge clk1) begin
+					pop = 1;
+				end
 			end
+			done = 1'b1;
+			a = 0;
 		end
-		done = 1'b1;
-    a = 0;
 	end
-end
-"af1024x36_4098x9": begin
-	initial #(50) begin
-		// Write data
-		for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
-			@(negedge clk0) begin
-				din = {a[8],a[8],a[7:0],a[7:0],a[8],a[8],a[7:0],a[7:0]};
-				push = 1;
-			end
-			@(posedge clk0) begin
-				#(PERIOD/10) push = 0;
-			end
-		end
-		// Read data
-		read_test = 1;
-		for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
-			@(posedge clk1) begin
-        expected <= {a[10:2]};
-				#(PERIOD/10) pop = 0;
-				if ( dout !== expected) begin
-					$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, dout, expected, a);
-				end else begin
-					$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, dout, expected, a);
-				end
-			end
-      @(negedge clk1) begin
-				pop = 1;
-			end
-		end
-		done = 1'b1;
-    a = 0;
-  end
-end
-endcase
+	endcase
 
 	// Scan for simulation finish
 	always @(posedge clk1) begin
@@ -214,78 +214,78 @@
 	case (`STRINGIFY(`TOP))
 		"af4096x9_1024x36": begin
 			af4096x9_1024x36 #() afifo (
-        .DIN(din),
-        .PUSH(push),
-        .POP(pop),
-        .clock0(clk0),
-        .clock1(clk1),
-        .Async_Flush(flush),
-        .Almost_Full(almost_full),
-        .Almost_Empty(almost_empty),
-        .Full(full),
-        .Empty(empty),
-        .Full_Watermark(full_watermark),
-        .Empty_Watermark(empty_watermark),
-        .Overrun_Error(overrun_error),
-        .Underrun_Error(underrun_error),
-        .DOUT(dout)
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk0),
+				.clock1(clk1),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
 			);
 		end
 		"af2048x18_1024x36": begin
 			af2048x18_1024x36 #() afifo (
-        .DIN(din),
-        .PUSH(push),
-        .POP(pop),
-        .clock0(clk0),
-        .clock1(clk1),
-        .Async_Flush(flush),
-        .Almost_Full(almost_full),
-        .Almost_Empty(almost_empty),
-        .Full(full),
-        .Empty(empty),
-        .Full_Watermark(full_watermark),
-        .Empty_Watermark(empty_watermark),
-        .Overrun_Error(overrun_error),
-        .Underrun_Error(underrun_error),
-        .DOUT(dout)
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk0),
+				.clock1(clk1),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
 			);
 		end
 		"af2048x18_4098x9": begin
 			af2048x18_4098x9 #() afifo (
-        .DIN(din),
-        .PUSH(push),
-        .POP(pop),
-        .clock0(clk0),
-        .clock1(clk1),
-        .Async_Flush(flush),
-        .Almost_Full(almost_full),
-        .Almost_Empty(almost_empty),
-        .Full(full),
-        .Empty(empty),
-        .Full_Watermark(full_watermark),
-        .Empty_Watermark(empty_watermark),
-        .Overrun_Error(overrun_error),
-        .Underrun_Error(underrun_error),
-        .DOUT(dout)
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk0),
+				.clock1(clk1),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
 			);
 		end
 		"af1024x36_4098x9": begin
 			af1024x36_4098x9 #() afifo (
-        .DIN(din),
-        .PUSH(push),
-        .POP(pop),
-        .clock0(clk0),
-        .clock1(clk1),
-        .Async_Flush(flush),
-        .Almost_Full(almost_full),
-        .Almost_Empty(almost_empty),
-        .Full(full),
-        .Empty(empty),
-        .Full_Watermark(full_watermark),
-        .Empty_Watermark(empty_watermark),
-        .Overrun_Error(overrun_error),
-        .Underrun_Error(underrun_error),
-        .DOUT(dout)
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk0),
+				.clock1(clk1),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
 			);
 		end
 	endcase

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sdp/sim/Makefile b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sdp/sim/Makefile
index fc7c0e9..88ba3d5 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sdp/sim/Makefile
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sdp/sim/Makefile

@@ -1,10 +1,18 @@
-# Copyright (C) 2019-2022 The SymbiFlow Authors
+# Copyright 2020-2022 F4PGA Authors
 #
-# Use of this source code is governed by a ISC-style
-# license that can be found in the LICENSE file or at
-# https://opensource.org/licenses/ISC
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
 #
-# SPDX-License-Identifier: ISC
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
 
 TESTBENCH = asymmetric_bram36k_sdp_tb.v
 POST_SYNTH = spram_9x4096_36x1024_post_synth spram_18x2048_36x1024_post_synth spram_18x2048_9x4096_post_synth spram_36x1024_18x2048_post_synth
@@ -31,7 +39,6 @@
 	@rm -rf  $(word $(1),$(POST_SYNTH)).vcd $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).vvp.log $(word $(1),$(POST_SYNTH)).vcd.log
 endef
 
-#FIXME: $(call simulate_post_synth,3)
 sim:
 	$(call simulate_post_synth,1)
 	$(call clean_post_synth_sim,1)

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sdp/sim/asymmetric_bram36k_sdp_tb.v b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sdp/sim/asymmetric_bram36k_sdp_tb.v
index 6ddc6c7..38064a3 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sdp/sim/asymmetric_bram36k_sdp_tb.v
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sdp/sim/asymmetric_bram36k_sdp_tb.v

@@ -4,7 +4,7 @@
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
 //
-//     http://www.apache.org/licenses/LICENSE-2.0
+//		 http://www.apache.org/licenses/LICENSE-2.0
 //
 // Unless required by applicable law or agreed to in writing, software
 // distributed under the License is distributed on an "AS IS" BASIS,
@@ -23,7 +23,7 @@
 	localparam ADDR_INCR = 1;
 
 	reg clk_0;
-  reg clk_1;
+	reg clk_1;
 	reg rce;
 	reg [`ADDR_WIDTH1-1:0] ra;
 	wire [`DATA_WIDTH1-1:0] rq;
@@ -34,12 +34,11 @@
 	initial clk_0 = 0;
 	initial clk_1 = 0;
 	initial ra = 0;
-  initial wa = 0;
-  initial wd = 0;
+	initial wa = 0;
+	initial wd = 0;
 	initial rce = 0;
-  initial wce = 0;
+	initial wce = 0;
 	initial forever #(PERIOD / 2.0) clk_0 = ~clk_0;
-  //initial forever #(PERIOD / 2.0) clk_1 = ~clk_1;
 	initial begin
 		#(PERIOD / 4.0);
 		forever #(PERIOD / 2.0) clk_1 = ~clk_1;
@@ -72,144 +71,144 @@
 			error_0_cnt <= error_0_cnt + 1'b1;
 	end
 
-case (`STRINGIFY(`TOP))
-"spram_9x4096_36x1024": begin
-	initial #(1) begin
-		// Write data
-		for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
-			@(negedge clk_0) begin
-				wa = a[`ADDR_WIDTH0-1:0];
-				wd = a[10:2];
-				wce = 1;
-			end
-			@(posedge clk_0) begin
-				#(PERIOD/10) wce = 0;
-			end
-		end
-		// Read data
-		read_test_0 = 1;
-		for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
-			@(negedge clk_1) begin
-				ra = a;
-				rce = 1;
-			end
-			@(posedge clk_1) begin
-        expected_0 <= {a[8],a[8],a[7:0],a[7:0],a[8],a[8],a[7:0],a[7:0]};
-				#(PERIOD/10) rce = 0;
-				if ( rq !== expected_0) begin
-					$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, rq, expected_0, a);
-				end else begin
-					$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, rq, expected_0, a);
+	case (`STRINGIFY(`TOP))
+	"spram_9x4096_36x1024": begin
+		initial #(1) begin
+			// Write data
+			for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
+				@(negedge clk_0) begin
+					wa = a[`ADDR_WIDTH0-1:0];
+					wd = a[10:2];
+					wce = 1;
+				end
+				@(posedge clk_0) begin
+					#(PERIOD/10) wce = 0;
 				end
 			end
+			// Read data
+			read_test_0 = 1;
+			for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
+				@(negedge clk_1) begin
+					ra = a;
+					rce = 1;
+				end
+				@(posedge clk_1) begin
+					expected_0 <= {a[8],a[8],a[7:0],a[7:0],a[8],a[8],a[7:0],a[7:0]};
+					#(PERIOD/10) rce = 0;
+					if ( rq !== expected_0) begin
+						$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, rq, expected_0, a);
+					end else begin
+						$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, rq, expected_0, a);
+					end
+				end
+			end
+			done_0 = 1'b1;
+			a = 0;
 		end
-		done_0 = 1'b1;
-    a = 0;
 	end
-end
-"spram_18x2048_36x1024": begin
-	initial #(1) begin
-		// Write data
-		for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
-			@(negedge clk_0) begin
-				wa = a[`ADDR_WIDTH0-1:0];
-				wd = a[18:1];
-				wce = 1;
-			end
-			@(posedge clk_0) begin
-				#(PERIOD/10) wce = 0;
-			end
-		end
-		// Read data
-		read_test_0 = 1;
-		for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
-			@(negedge clk_1) begin
-				ra = a;
-				rce = 1;
-			end
-			@(posedge clk_1) begin
-        expected_0 <= {a[17:0],a[17:0]};
-				#(PERIOD/10) rce = 0;
-				if ( rq !== expected_0) begin
-					$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, rq, expected_0, a);
-				end else begin
-					$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, rq, expected_0, a);
+	"spram_18x2048_36x1024": begin
+		initial #(1) begin
+			// Write data
+			for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
+				@(negedge clk_0) begin
+					wa = a[`ADDR_WIDTH0-1:0];
+					wd = a[18:1];
+					wce = 1;
+				end
+				@(posedge clk_0) begin
+					#(PERIOD/10) wce = 0;
 				end
 			end
+			// Read data
+			read_test_0 = 1;
+			for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
+				@(negedge clk_1) begin
+					ra = a;
+					rce = 1;
+				end
+				@(posedge clk_1) begin
+					expected_0 <= {a[17:0],a[17:0]};
+					#(PERIOD/10) rce = 0;
+					if ( rq !== expected_0) begin
+						$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, rq, expected_0, a);
+					end else begin
+						$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, rq, expected_0, a);
+					end
+				end
+			end
+			done_0 = 1'b1;
+			a = 0;
 		end
-		done_0 = 1'b1;
-    a = 0;
+	end	 
+	"spram_18x2048_9x4096": begin
+		initial #(1) begin
+			// Write data
+			for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
+				@(negedge clk_0) begin
+					wa = a[`ADDR_WIDTH0-1:0];
+					wd = {a[8],a[8],a[7:0],a[7:0]};
+					wce = 1;
+				end
+				@(posedge clk_0) begin
+					#(PERIOD/10) wce = 0;
+				end
+			end
+			// Read data
+			read_test_0 = 1;
+			for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
+				@(negedge clk_1) begin
+					ra = a;
+					rce = 1;
+				end
+				@(posedge clk_1) begin
+					expected_0 <= {a[9:1]};
+					#(PERIOD/10) rce = 0;
+					if ( rq !== expected_0) begin
+						$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, rq, expected_0, a);
+					end else begin
+						$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, rq, expected_0, a);
+					end
+				end
+			end
+			done_0 = 1'b1;
+			a = 0;
+		end
 	end
-end  
-"spram_18x2048_9x4096": begin
-	initial #(1) begin
-		// Write data
-		for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
-			@(negedge clk_0) begin
-				wa = a[`ADDR_WIDTH0-1:0];
-				wd = {a[8],a[8],a[7:0],a[7:0]};
-				wce = 1;
-			end
-			@(posedge clk_0) begin
-				#(PERIOD/10) wce = 0;
-			end
-		end
-		// Read data
-		read_test_0 = 1;
-		for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
-			@(negedge clk_1) begin
-				ra = a;
-				rce = 1;
-			end
-			@(posedge clk_1) begin
-        expected_0 <= {a[9:1]};
-				#(PERIOD/10) rce = 0;
-				if ( rq !== expected_0) begin
-					$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, rq, expected_0, a);
-				end else begin
-					$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, rq, expected_0, a);
+	"spram_36x1024_18x2048": begin
+		initial #(1) begin
+			// Write data
+			for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
+				@(negedge clk_0) begin
+					wa = a[`ADDR_WIDTH0-1:0];
+					wd = {a[17:0],a[17:0]};
+					wce = 1;
+				end
+				@(posedge clk_0) begin
+					#(PERIOD/10) wce = 0;
 				end
 			end
+			// Read data
+			read_test_0 = 1;
+			for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
+				@(negedge clk_1) begin
+					ra = a;
+					rce = 1;
+				end
+				@(posedge clk_1) begin
+					expected_0 <= {a[18:1]};
+					#(PERIOD/10) rce = 0;
+					if ( rq !== expected_0) begin
+						$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, rq, expected_0, a);
+					end else begin
+						$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, rq, expected_0, a);
+					end
+				end
+			end
+			done_0 = 1'b1;
+			a = 0;
 		end
-		done_0 = 1'b1;
-    a = 0;
 	end
-end
-"spram_36x1024_18x2048": begin
-	initial #(1) begin
-		// Write data
-		for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
-			@(negedge clk_0) begin
-				wa = a[`ADDR_WIDTH0-1:0];
-				wd = {a[17:0],a[17:0]};
-				wce = 1;
-			end
-			@(posedge clk_0) begin
-				#(PERIOD/10) wce = 0;
-			end
-		end
-		// Read data
-		read_test_0 = 1;
-		for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
-			@(negedge clk_1) begin
-				ra = a;
-				rce = 1;
-			end
-			@(posedge clk_1) begin
-        expected_0 <= {a[18:1]};
-				#(PERIOD/10) rce = 0;
-				if ( rq !== expected_0) begin
-					$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, rq, expected_0, a);
-				end else begin
-					$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, rq, expected_0, a);
-				end
-			end
-		end
-		done_0 = 1'b1;
-    a = 0;
-  end
-end
-endcase
+	endcase
 
 	// Scan for simulation finish
 	always @(posedge clk_1) begin
@@ -221,7 +220,7 @@
 		"spram_9x4096_36x1024": begin
 			spram_9x4096_36x1024 #() bram (
 				.clock0(clk_0),
-        .clock1(clk_1),        
+				.clock1(clk_1),				 
 				.REN_i(rce),
 				.RD_ADDR_i(ra),
 				.RDATA_o(rq),
@@ -233,7 +232,7 @@
 		"spram_18x2048_36x1024": begin
 			spram_18x2048_36x1024 #() bram (
 				.clock0(clk_0),
-        .clock1(clk_1),        
+				.clock1(clk_1),				 
 				.REN_i(rce),
 				.RD_ADDR_i(ra),
 				.RDATA_o(rq),
@@ -245,7 +244,7 @@
 		"spram_18x2048_9x4096": begin
 			spram_18x2048_9x4096 #() bram (
 				.clock0(clk_0),
-        .clock1(clk_1),        
+				.clock1(clk_1),				 
 				.REN_i(rce),
 				.RD_ADDR_i(ra),
 				.RDATA_o(rq),
@@ -257,7 +256,7 @@
 		"spram_36x1024_18x2048": begin
 			spram_36x1024_18x2048 #() bram (
 				.clock0(clk_0),
-        .clock1(clk_1),        
+				.clock1(clk_1),				 
 				.REN_i(rce),
 				.RD_ADDR_i(ra),
 				.RDATA_o(rq),

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sfifo/asymmetric_bram36k_sfifo.v b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sfifo/asymmetric_bram36k_sfifo.v
index fd01e93..c0b6507 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sfifo/asymmetric_bram36k_sfifo.v
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sfifo/asymmetric_bram36k_sfifo.v

@@ -32,7 +32,7 @@
 output Overrun_Error, Underrun_Error;
 
 SFIFO_36K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
-        				 ) 
+                  )
   FIFO_INST    (
                 .DIN(DIN),
                 .PUSH(PUSH),
@@ -51,8 +51,7 @@
                 .Empty(Empty),
 
                 .DOUT(DOUT)
-         				);
-
+                );
 endmodule
 
 module f2048x18_1024x36 (DIN,PUSH,POP,clock0,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
@@ -73,7 +72,7 @@
 output Overrun_Error, Underrun_Error;
 
 SFIFO_36K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
-        				 ) 
+                  )
   FIFO_INST    (
                 .DIN(DIN),
                 .PUSH(PUSH),
@@ -92,8 +91,7 @@
                 .Empty(Empty),
 
                 .DOUT(DOUT)
-         				);
-
+                );
 endmodule
 
 module f2048x18_4098x9 (DIN,PUSH,POP,clock0,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
@@ -114,7 +112,7 @@
 output Overrun_Error, Underrun_Error;
 
 SFIFO_36K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
-        				 ) 
+                  )
   FIFO_INST    (
                 .DIN(DIN),
                 .PUSH(PUSH),
@@ -133,8 +131,7 @@
                 .Empty(Empty),
 
                 .DOUT(DOUT)
-         				);
-
+                );
 endmodule
 
 module f1024x36_2048x18 (DIN,PUSH,POP,clock0,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
@@ -155,7 +152,7 @@
 output Overrun_Error, Underrun_Error;
 
 SFIFO_36K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
-        				 ) 
+                  )
   FIFO_INST    (
                 .DIN(DIN),
                 .PUSH(PUSH),
@@ -174,6 +171,5 @@
                 .Empty(Empty),
 
                 .DOUT(DOUT)
-         				);
-
+                );
 endmodule
\ No newline at end of file

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sfifo/sim/Makefile b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sfifo/sim/Makefile
index a015284..e13baa3 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sfifo/sim/Makefile
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sfifo/sim/Makefile

@@ -39,7 +39,6 @@
 	@rm -rf  $(word $(1),$(POST_SYNTH)).vcd $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).vvp.log $(word $(1),$(POST_SYNTH)).vcd.log
 endef
 
-#FIXME: $(call simulate_post_synth,3)
 sim:
 	$(call simulate_post_synth,1)
 	$(call clean_post_synth_sim,1)

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sfifo/sim/asymmetric_bram36k_sfifo_tb.v b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sfifo/sim/asymmetric_bram36k_sfifo_tb.v
index ba6775d..b1c753c 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sfifo/sim/asymmetric_bram36k_sfifo_tb.v
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/asymmetric_bram36k_sfifo/sim/asymmetric_bram36k_sfifo_tb.v

@@ -4,7 +4,7 @@
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
 //
-//     http://www.apache.org/licenses/LICENSE-2.0
+//		 http://www.apache.org/licenses/LICENSE-2.0
 //
 // Unless required by applicable law or agreed to in writing, software
 // distributed under the License is distributed on an "AS IS" BASIS,
@@ -23,29 +23,29 @@
 	localparam ADDR_INCR = 1;
 
 	reg clk0;
-  reg flush;
+	reg flush;
 	reg pop;
 	wire [`DATA_WIDTH1-1:0] dout;
 	reg push;
 	reg [`DATA_WIDTH0-1:0] din;
-  wire almost_full,almost_empty;
-  wire full, empty;
-  wire full_watermark, empty_watermark;
-  wire overrun_error, underrun_error;
+	wire almost_full,almost_empty;
+	wire full, empty;
+	wire full_watermark, empty_watermark;
+	wire overrun_error, underrun_error;
 
-  initial 
-  begin
-    clk0 = 0;
-    pop = 0;
-    push = 0;
-    flush = 1;
-    din = 0;
-    #40
-    flush = 0;
-  end
-  
+	initial 
+	begin
+		clk0 = 0;
+		pop = 0;
+		push = 0;
+		flush = 1;
+		din = 0;
+		#40
+		flush = 0;
+	end
+	
 	initial forever #(PERIOD / 3.0) clk0 = ~clk0;
-  
+	
 	initial begin
 		$dumpfile(`STRINGIFY(`VCD));
 		$dumpvars;
@@ -55,12 +55,12 @@
 
 	reg done;
 	initial done = 1'b0;
-  
-  reg read_test;
+	
+	reg read_test;
 	initial read_test = 0;
 
 	reg [`DATA_WIDTH1-1:0] expected;
-  initial expected = 0;
+	initial expected = 0;
 
 	wire error = (read_test) ? dout !== expected : 0;
 
@@ -71,136 +71,136 @@
 			error_cnt <= error_cnt + 1'b1; 
 	end
 
-case (`STRINGIFY(`TOP))
-"f4096x9_1024x36": begin
-	initial #(50) begin
-		// Write data
-		for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
-			@(negedge clk0) begin
-				din = a[10:2];
-				push = 1;
-			end
-			@(posedge clk0) begin
-				#(PERIOD/10) push = 0;
-			end
-		end
-		// Read data
-		read_test = 1;
-		for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
-			@(posedge clk0) begin
-        expected <= {a[8],a[8],a[7:0],a[7:0],a[8],a[8],a[7:0],a[7:0]};
-				#(PERIOD/10) pop = 0;
-				if ( dout !== expected) begin
-					$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, dout, expected, a);
-				end else begin
-					$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, dout, expected, a);
+	case (`STRINGIFY(`TOP))
+	"f4096x9_1024x36": begin
+		initial #(50) begin
+			// Write data
+			for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
+				@(negedge clk0) begin
+					din = a[10:2];
+					push = 1;
+				end
+				@(posedge clk0) begin
+					#(PERIOD/10) push = 0;
 				end
 			end
-      @(negedge clk0) begin
-				pop = 1;
+			// Read data
+			read_test = 1;
+			for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
+				@(posedge clk0) begin
+					expected <= {a[8],a[8],a[7:0],a[7:0],a[8],a[8],a[7:0],a[7:0]};
+					#(PERIOD/10) pop = 0;
+					if ( dout !== expected) begin
+						$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, dout, expected, a);
+					end else begin
+						$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, dout, expected, a);
+					end
+				end
+				@(negedge clk0) begin
+					pop = 1;
+				end
 			end
+			done = 1'b1;
+			a = 0;
 		end
-		done = 1'b1;
-    a = 0;
 	end
-end
-"f2048x18_1024x36": begin
-	initial #(50) begin
-		// Write data
-		for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
-			@(negedge clk0) begin
-				din = a[18:1];
-				push = 1;
-			end
-			@(posedge clk0) begin
-				#(PERIOD/10) push = 0;
-			end
-		end
-		// Read data
-		read_test = 1;
-		for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
-			@(posedge clk0) begin
-        expected <= {a[17:0],a[17:0]};
-				#(PERIOD/10) pop = 0;
-				if ( dout !== expected) begin
-					$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, dout, expected, a);
-				end else begin
-					$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, dout, expected, a);
+	"f2048x18_1024x36": begin
+		initial #(50) begin
+			// Write data
+			for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
+				@(negedge clk0) begin
+					din = a[18:1];
+					push = 1;
+				end
+				@(posedge clk0) begin
+					#(PERIOD/10) push = 0;
 				end
 			end
-      @(negedge clk0) begin
-				pop = 1;
+			// Read data
+			read_test = 1;
+			for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
+				@(posedge clk0) begin
+					expected <= {a[17:0],a[17:0]};
+					#(PERIOD/10) pop = 0;
+					if ( dout !== expected) begin
+						$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, dout, expected, a);
+					end else begin
+						$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, dout, expected, a);
+					end
+				end
+				@(negedge clk0) begin
+					pop = 1;
+				end
 			end
+			done = 1'b1;
+			a = 0;
 		end
-		done = 1'b1;
-    a = 0;
+	end	 
+	"f2048x18_4098x9": begin
+		initial #(50) begin
+			// Write data
+			for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
+				@(negedge clk0) begin
+					din = {a[8],a[8],a[7:0],a[7:0]};
+					push = 1;
+				end
+				@(posedge clk0) begin
+					#(PERIOD/10) push = 0;
+				end
+			end
+			// Read data
+			read_test = 1;
+			for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
+				@(posedge clk0) begin
+					expected <= {a[9:1]};
+					#(PERIOD/10) pop = 0;
+					if ( dout !== expected) begin
+						$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, dout, expected, a);
+					end else begin
+						$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, dout, expected, a);
+					end
+				end
+				@(negedge clk0) begin
+					pop = 1;
+				end
+			end
+			done = 1'b1;
+			a = 0;
+		end
 	end
-end  
-"f2048x18_4098x9": begin
-	initial #(50) begin
-		// Write data
-		for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
-			@(negedge clk0) begin
-				din = {a[8],a[8],a[7:0],a[7:0]};
-				push = 1;
-			end
-			@(posedge clk0) begin
-				#(PERIOD/10) push = 0;
-			end
-		end
-		// Read data
-		read_test = 1;
-		for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
-			@(posedge clk0) begin
-        expected <= {a[9:1]};
-				#(PERIOD/10) pop = 0;
-				if ( dout !== expected) begin
-					$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, dout, expected, a);
-				end else begin
-					$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, dout, expected, a);
+	"f1024x36_2048x18": begin
+		initial #(50) begin
+			// Write data
+			for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
+				@(negedge clk0) begin
+					din = {a[17:0],a[17:0]};
+					push = 1;
+				end
+				@(posedge clk0) begin
+					#(PERIOD/10) push = 0;
 				end
 			end
-      @(negedge clk0) begin
-				pop = 1;
+			// Read data
+			read_test = 1;
+			for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
+				@(posedge clk0) begin
+					expected <= {a[18:1]};
+					#(PERIOD/10) pop = 0;
+					if ( dout !== expected) begin
+						$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, dout, expected, a);
+					end else begin
+						$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, dout, expected, a);
+					end
+				end
+				@(negedge clk0) begin
+					pop = 1;
+				end
 			end
+			done = 1'b1;
+			a = 0;
 		end
-		done = 1'b1;
-    a = 0;
 	end
-end
-"f1024x36_2048x18": begin
-	initial #(50) begin
-		// Write data
-		for (a = 0; a < (1<<`ADDR_WIDTH0) ; a = a + ADDR_INCR) begin
-			@(negedge clk0) begin
-				din = {a[17:0],a[17:0]};
-				push = 1;
-			end
-			@(posedge clk0) begin
-				#(PERIOD/10) push = 0;
-			end
-		end
-		// Read data
-		read_test = 1;
-		for (a = 0; a < (1<<`ADDR_WIDTH1); a = a + ADDR_INCR) begin
-			@(posedge clk0) begin
-        expected <= {a[18:1]};
-				#(PERIOD/10) pop = 0;
-				if ( dout !== expected) begin
-					$display("%d: PORT 0: FAIL: mismatch act=%x exp=%x at %x", $time, dout, expected, a);
-				end else begin
-					$display("%d: PORT 0: OK: act=%x exp=%x at %x", $time, dout, expected, a);
-				end
-			end
-      @(negedge clk0) begin
-				pop = 1;
-			end
-		end
-		done = 1'b1;
-    a = 0;
-  end
-end
-endcase
+	endcase
 
 	// Scan for simulation finish
 	always @(posedge clk0) begin
@@ -211,74 +211,74 @@
 	case (`STRINGIFY(`TOP))
 		"f4096x9_1024x36": begin
 			f4096x9_1024x36 #() afifo (
-        .DIN(din),
-        .PUSH(push),
-        .POP(pop),
-        .clock0(clk0),
-        .Async_Flush(flush),
-        .Almost_Full(almost_full),
-        .Almost_Empty(almost_empty),
-        .Full(full),
-        .Empty(empty),
-        .Full_Watermark(full_watermark),
-        .Empty_Watermark(empty_watermark),
-        .Overrun_Error(overrun_error),
-        .Underrun_Error(underrun_error),
-        .DOUT(dout)
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk0),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
 			);
 		end
 		"f2048x18_1024x36": begin
 			f2048x18_1024x36 #() afifo (
-        .DIN(din),
-        .PUSH(push),
-        .POP(pop),
-        .clock0(clk0),
-        .Async_Flush(flush),
-        .Almost_Full(almost_full),
-        .Almost_Empty(almost_empty),
-        .Full(full),
-        .Empty(empty),
-        .Full_Watermark(full_watermark),
-        .Empty_Watermark(empty_watermark),
-        .Overrun_Error(overrun_error),
-        .Underrun_Error(underrun_error),
-        .DOUT(dout)
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk0),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
 			);
 		end
 		"f2048x18_4098x9": begin
 			f2048x18_4098x9 #() afifo (
-        .DIN(din),
-        .PUSH(push),
-        .POP(pop),
-        .clock0(clk0),
-        .Async_Flush(flush),
-        .Almost_Full(almost_full),
-        .Almost_Empty(almost_empty),
-        .Full(full),
-        .Empty(empty),
-        .Full_Watermark(full_watermark),
-        .Empty_Watermark(empty_watermark),
-        .Overrun_Error(overrun_error),
-        .Underrun_Error(underrun_error),
-        .DOUT(dout)
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk0),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
 			);
 		end
 		"f1024x36_2048x18": begin
 			f1024x36_2048x18 #() afifo (
-        .DIN(din),
-        .PUSH(push),
-        .POP(pop),
-        .clock0(clk0),
-        .Async_Flush(flush),
-        .Almost_Full(almost_full),
-        .Almost_Empty(almost_empty),
-        .Full(full),
-        .Empty(empty),
-        .Full_Watermark(full_watermark),
-        .Empty_Watermark(empty_watermark),
-        .Overrun_Error(overrun_error),
-        .Underrun_Error(underrun_error),
-        .DOUT(dout)
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk0),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
 			);
 		end
 	endcase

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_afifo/bram18k_afifo.v b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_afifo/bram18k_afifo.v
index e4aa0e9..bd1fa13 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_afifo/bram18k_afifo.v
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_afifo/bram18k_afifo.v

@@ -32,7 +32,7 @@
 output Overrun_Error, Underrun_Error;
 
 AFIFO_18K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
-        				 ) 
+                  )
   FIFO_INST    (
                 .DIN(DIN),
                 .PUSH(PUSH),
@@ -52,8 +52,7 @@
                 .Empty(Empty),
 
                 .DOUT(DOUT)
-         				);
-
+                );
 endmodule
 
 module af1024x16_1024x16 (DIN,PUSH,POP,clock0,clock1,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
@@ -74,7 +73,7 @@
 output Overrun_Error, Underrun_Error;
 
 AFIFO_18K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
-        				 ) 
+                  )
   FIFO_INST    (
                 .DIN(DIN),
                 .PUSH(PUSH),
@@ -94,8 +93,7 @@
                 .Empty(Empty),
 
                 .DOUT(DOUT)
-         				);
-
+                );
 endmodule
 
 module af2048x9_2048x9 (DIN,PUSH,POP,clock0,clock1,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
@@ -116,7 +114,7 @@
 output Overrun_Error, Underrun_Error;
 
 AFIFO_18K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
-        				 ) 
+                  )
   FIFO_INST    (
                 .DIN(DIN),
                 .PUSH(PUSH),
@@ -136,8 +134,7 @@
                 .Empty(Empty),
 
                 .DOUT(DOUT)
-         				);
-
+                );
 endmodule
 
 module af2048x8_2048x8 (DIN,PUSH,POP,clock0,clock1,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
@@ -158,7 +155,7 @@
 output Overrun_Error, Underrun_Error;
 
 AFIFO_18K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
-        				 ) 
+                  )
   FIFO_INST    (
                 .DIN(DIN),
                 .PUSH(PUSH),
@@ -178,6 +175,5 @@
                 .Empty(Empty),
 
                 .DOUT(DOUT)
-         				);
-
+                );
 endmodule
\ No newline at end of file

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_afifo/sim/Makefile b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_afifo/sim/Makefile
index 0153897..3c2bce7 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_afifo/sim/Makefile
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_afifo/sim/Makefile

@@ -39,7 +39,6 @@
 	@rm -rf  $(word $(1),$(POST_SYNTH)).vcd $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).vvp.log $(word $(1),$(POST_SYNTH)).vcd.log
 endef
 
-# FIXME: $(call simulate_post_synth,5)
 sim:
 	$(call simulate_post_synth,1)
 	$(call clean_post_synth_sim,1)

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_afifo/sim/bram18k_afifo_tb.v b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_afifo/sim/bram18k_afifo_tb.v
index 62460b1..1795312 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_afifo/sim/bram18k_afifo_tb.v
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_afifo/sim/bram18k_afifo_tb.v

@@ -4,7 +4,7 @@
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
 //
-//     http://www.apache.org/licenses/LICENSE-2.0
+//		 http://www.apache.org/licenses/LICENSE-2.0
 //
 // Unless required by applicable law or agreed to in writing, software
 // distributed under the License is distributed on an "AS IS" BASIS,
@@ -23,32 +23,32 @@
 	localparam ADDR_INCR = 1;
 
 	reg clk0;
-  reg clk1;
-  reg flush;
+	reg clk1;
+	reg flush;
 	reg pop;
 	wire [`DATA_WIDTH1-1:0] dout;
 	reg push;
 	reg [`DATA_WIDTH0-1:0] din;
-  wire almost_full,almost_empty;
-  wire full, empty;
-  wire full_watermark, empty_watermark;
-  wire overrun_error, underrun_error;
+	wire almost_full,almost_empty;
+	wire full, empty;
+	wire full_watermark, empty_watermark;
+	wire overrun_error, underrun_error;
 
-  initial 
-  begin
-    clk0 = 0;
-    clk1 = 0;
-    pop = 0;
-    push = 0;
-    flush = 1;
-    din = 0;
-    #40
-    flush = 0;
-  end
-  
+	initial 
+	begin
+		clk0 = 0;
+		clk1 = 0;
+		pop = 0;
+		push = 0;
+		flush = 1;
+		din = 0;
+		#40
+		flush = 0;
+	end
+	
 	initial forever #(PERIOD / 3.0) clk0 = ~clk0;
-  initial forever #(PERIOD / 2.0) clk1 = ~clk1;
-  
+	initial forever #(PERIOD / 2.0) clk1 = ~clk1;
+	
 	initial begin
 		$dumpfile(`STRINGIFY(`VCD));
 		$dumpvars;
@@ -63,7 +63,7 @@
 	initial read_test = 0;
 
 	reg [`DATA_WIDTH1-1:0] expected;
-  initial expected = 0;
+	initial expected = 0;
 
 	always @(posedge clk1) begin
 		expected <= (a | (a << 20) | 20'h55000) & {`DATA_WIDTH1{1'b1}};
@@ -79,7 +79,7 @@
 	end
 
 	initial #(50) begin
-    @(posedge clk0)
+		@(posedge clk0)
 		// Write data
 		for (a = 0; a < (1<<`ADDR_WIDTH0); a = a + ADDR_INCR) begin
 			@(negedge clk0) begin
@@ -117,78 +117,78 @@
 	case (`STRINGIFY(`TOP))
 		"af1024x18_1024x18": begin
 			af1024x18_1024x18 #() afifo (
-        .DIN(din),
-        .PUSH(push),
-        .POP(pop),
-        .clock0(clk0),
-        .clock1(clk1),
-        .Async_Flush(flush),
-        .Almost_Full(almost_full),
-        .Almost_Empty(almost_empty),
-        .Full(full),
-        .Empty(empty),
-        .Full_Watermark(full_watermark),
-        .Empty_Watermark(empty_watermark),
-        .Overrun_Error(overrun_error),
-        .Underrun_Error(underrun_error),
-        .DOUT(dout)
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk0),
+				.clock1(clk1),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
 			);
 		end
 		"af1024x16_1024x16": begin
 			af1024x16_1024x16 #() afifo (
-        .DIN(din),
-        .PUSH(push),
-        .POP(pop),
-        .clock0(clk0),
-        .clock1(clk1),
-        .Async_Flush(flush),
-        .Almost_Full(almost_full),
-        .Almost_Empty(almost_empty),
-        .Full(full),
-        .Empty(empty),
-        .Full_Watermark(full_watermark),
-        .Empty_Watermark(empty_watermark),
-        .Overrun_Error(overrun_error),
-        .Underrun_Error(underrun_error),
-        .DOUT(dout)
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk0),
+				.clock1(clk1),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
 			);
 		end
 		"af2048x9_2048x9": begin
 			af2048x9_2048x9 #() afifo (
-        .DIN(din),
-        .PUSH(push),
-        .POP(pop),
-        .clock0(clk0),
-        .clock1(clk1),
-        .Async_Flush(flush),
-        .Almost_Full(almost_full),
-        .Almost_Empty(almost_empty),
-        .Full(full),
-        .Empty(empty),
-        .Full_Watermark(full_watermark),
-        .Empty_Watermark(empty_watermark),
-        .Overrun_Error(overrun_error),
-        .Underrun_Error(underrun_error),
-        .DOUT(dout)
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk0),
+				.clock1(clk1),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
 			);
 		end		
 		"af2048x8_2048x8": begin
 			af2048x8_2048x8 #() afifo (
-        .DIN(din),
-        .PUSH(push),
-        .POP(pop),
-        .clock0(clk0),
-        .clock1(clk1),
-        .Async_Flush(flush),
-        .Almost_Full(almost_full),
-        .Almost_Empty(almost_empty),
-        .Full(full),
-        .Empty(empty),
-        .Full_Watermark(full_watermark),
-        .Empty_Watermark(empty_watermark),
-        .Overrun_Error(overrun_error),
-        .Underrun_Error(underrun_error),
-        .DOUT(dout)
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk0),
+				.clock1(clk1),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
 			);
 		end	
 	endcase

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sdp/sim/Makefile b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sdp/sim/Makefile
index 4a8ae5e..aeb9aec 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sdp/sim/Makefile
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sdp/sim/Makefile

@@ -39,7 +39,6 @@
 	@rm -rf  $(word $(1),$(POST_SYNTH)).vcd $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).vvp.log $(word $(1),$(POST_SYNTH)).vcd.log
 endef
 
-#FIXME: $(call simulate_post_synth,3)
 sim:
 	$(call simulate_post_synth,1)
 	$(call clean_post_synth_sim,1)

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sdp/sim/bram18k_sdp_tb.v b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sdp/sim/bram18k_sdp_tb.v
index 1294edd..8d91922 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sdp/sim/bram18k_sdp_tb.v
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sdp/sim/bram18k_sdp_tb.v

@@ -4,7 +4,7 @@
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
 //
-//     http://www.apache.org/licenses/LICENSE-2.0
+//		 http://www.apache.org/licenses/LICENSE-2.0
 //
 // Unless required by applicable law or agreed to in writing, software
 // distributed under the License is distributed on an "AS IS" BASIS,
@@ -126,7 +126,7 @@
 			end
 		end
 		done_0 = 1'b1;
-    a = 0;
+		a = 0;
 	end
 
 	// PART 1
@@ -159,7 +159,7 @@
 			end
 		end
 		done_1 = 1'b1;
-    b = (1<<`ADDR_WIDTH1) / 2;
+		b = (1<<`ADDR_WIDTH1) / 2;
 	end
 
 	// Scan for simulation finish

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sfifo/bram18k_sfifo.v b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sfifo/bram18k_sfifo.v
index d018b00..c559134 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sfifo/bram18k_sfifo.v
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sfifo/bram18k_sfifo.v

@@ -32,7 +32,7 @@
 output Overrun_Error, Underrun_Error;
 
 SFIFO_18K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
-        				 ) 
+                  )
   FIFO_INST    (
                 .DIN(DIN),
                 .PUSH(PUSH),
@@ -51,8 +51,7 @@
                 .Empty(Empty),
 
                 .DOUT(DOUT)
-         				);
-
+                );
 endmodule
 
 module f1024x16_1024x16 (DIN,PUSH,POP,clock0,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
@@ -73,7 +72,7 @@
 output Overrun_Error, Underrun_Error;
 
 SFIFO_18K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
-        				 ) 
+                  )
   FIFO_INST    (
                 .DIN(DIN),
                 .PUSH(PUSH),
@@ -92,8 +91,7 @@
                 .Empty(Empty),
 
                 .DOUT(DOUT)
-         				);
-
+                );
 endmodule
 
 module f2048x9_2048x9 (DIN,PUSH,POP,clock0,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
@@ -114,7 +112,7 @@
 output Overrun_Error, Underrun_Error;
 
 SFIFO_18K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
-        				 ) 
+                  )
   FIFO_INST    (
                 .DIN(DIN),
                 .PUSH(PUSH),
@@ -133,8 +131,7 @@
                 .Empty(Empty),
 
                 .DOUT(DOUT)
-         				);
-
+                );
 endmodule
 
 module f2048x8_2048x8 (DIN,PUSH,POP,clock0,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
@@ -155,7 +152,7 @@
 output Overrun_Error, Underrun_Error;
 
 SFIFO_18K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
-        				 ) 
+                  )
   FIFO_INST    (
                 .DIN(DIN),
                 .PUSH(PUSH),
@@ -174,6 +171,5 @@
                 .Empty(Empty),
 
                 .DOUT(DOUT)
-         				);
-
+                );
 endmodule
\ No newline at end of file

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sfifo/sim/Makefile b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sfifo/sim/Makefile
index 2a46d29..86a1b10 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sfifo/sim/Makefile
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sfifo/sim/Makefile

@@ -39,7 +39,6 @@
 	@rm -rf  $(word $(1),$(POST_SYNTH)).vcd $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).vvp.log $(word $(1),$(POST_SYNTH)).vcd.log
 endef
 
-# FIXME: $(call simulate_post_synth,5)
 sim:
 	$(call simulate_post_synth,1)
 	$(call clean_post_synth_sim,1)

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sfifo/sim/bram18k_sfifo_tb.v b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sfifo/sim/bram18k_sfifo_tb.v
index f5c56cf..579d881 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sfifo/sim/bram18k_sfifo_tb.v
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_sfifo/sim/bram18k_sfifo_tb.v

@@ -4,7 +4,7 @@
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
 //
-//     http://www.apache.org/licenses/LICENSE-2.0
+//		 http://www.apache.org/licenses/LICENSE-2.0
 //
 // Unless required by applicable law or agreed to in writing, software
 // distributed under the License is distributed on an "AS IS" BASIS,
@@ -23,29 +23,29 @@
 	localparam ADDR_INCR = 1;
 
 	reg clk;
-  reg flush;
+	reg flush;
 	reg pop;
 	wire [`DATA_WIDTH1-1:0] dout;
 	reg push;
 	reg [`DATA_WIDTH0-1:0] din;
-  wire almost_full,almost_empty;
-  wire full, empty;
-  wire full_watermark, empty_watermark;
-  wire overrun_error, underrun_error;
+	wire almost_full,almost_empty;
+	wire full, empty;
+	wire full_watermark, empty_watermark;
+	wire overrun_error, underrun_error;
 
-  initial 
-  begin
-    clk = 0;
-    pop = 0;
-    push = 0;
-    flush = 1;
-    din = 0;
-    #40
-    flush = 0;
-  end
-  
+	initial 
+	begin
+		clk = 0;
+		pop = 0;
+		push = 0;
+		flush = 1;
+		din = 0;
+		#40
+		flush = 0;
+	end
+	
 	initial forever #(PERIOD / 3.0) clk = ~clk;
-  
+	
 	initial begin
 		$dumpfile(`STRINGIFY(`VCD));
 		$dumpvars;
@@ -55,12 +55,12 @@
 
 	reg done;
 	initial done = 1'b0;
-  
+	
 	reg read_test;
 	initial read_test = 0;
 
 	reg [`DATA_WIDTH1-1:0] expected;
-  initial expected = 0;
+	initial expected = 0;
 
 	always @(posedge clk) begin
 		expected <= (a | (a << 20) | 20'h55000) & {`DATA_WIDTH1{1'b1}};
@@ -76,7 +76,7 @@
 	end
 
 	initial #(50) begin
-    @(posedge clk)
+		@(posedge clk)
 		// Write data
 		for (a = 0; a < (1<<`ADDR_WIDTH0); a = a + ADDR_INCR) begin
 			@(negedge clk) begin
@@ -114,75 +114,75 @@
 	case (`STRINGIFY(`TOP))
 		"f1024x18_1024x18": begin
 			f1024x18_1024x18 #() afifo (
-        .DIN(din),
-        .PUSH(push),
-        .POP(pop),
-        .clock0(clk),
-        .Async_Flush(flush),
-        .Almost_Full(almost_full),
-        .Almost_Empty(almost_empty),
-        .Full(full),
-        .Empty(empty),
-        .Full_Watermark(full_watermark),
-        .Empty_Watermark(empty_watermark),
-        .Overrun_Error(overrun_error),
-        .Underrun_Error(underrun_error),
-        .DOUT(dout)
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
 			);
 		end
 		"f1024x16_1024x16": begin
 			f1024x16_1024x16 #() afifo (
-        .DIN(din),
-        .PUSH(push),
-        .POP(pop),
-        .clock0(clk),
-        .Async_Flush(flush),
-        .Almost_Full(almost_full),
-        .Almost_Empty(almost_empty),
-        .Full(full),
-        .Empty(empty),
-        .Full_Watermark(full_watermark),
-        .Empty_Watermark(empty_watermark),
-        .Overrun_Error(overrun_error),
-        .Underrun_Error(underrun_error),
-        .DOUT(dout)
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
 			);
 		end
 		"f2048x9_2048x9": begin
 			f2048x9_2048x9 #() afifo (
-        .DIN(din),
-        .PUSH(push),
-        .POP(pop),
-        .clock0(clk),
-        .Async_Flush(flush),
-        .Almost_Full(almost_full),
-        .Almost_Empty(almost_empty),
-        .Full(full),
-        .Empty(empty),
-        .Full_Watermark(full_watermark),
-        .Empty_Watermark(empty_watermark),
-        .Overrun_Error(overrun_error),
-        .Underrun_Error(underrun_error),
-        .DOUT(dout)
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
 			);
 		end	
 		"f2048x8_2048x8": begin
 			f2048x8_2048x8 #() afifo (
-        .DIN(din),
-        .PUSH(push),
-        .POP(pop),
-        .clock0(clk),
-        .Async_Flush(flush),
-        .Almost_Full(almost_full),
-        .Almost_Empty(almost_empty),
-        .Full(full),
-        .Empty(empty),
-        .Full_Watermark(full_watermark),
-        .Empty_Watermark(empty_watermark),
-        .Overrun_Error(overrun_error),
-        .Underrun_Error(underrun_error),
-        .DOUT(dout)
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
 			);
-		end	    
+		end			
 	endcase
 endmodule

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_tdp/sim/Makefile b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_tdp/sim/Makefile
index 83ea28e..b9883eb 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_tdp/sim/Makefile
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_tdp/sim/Makefile

@@ -39,7 +39,6 @@
 	@rm -rf  $(word $(1),$(POST_SYNTH)).vcd $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).vvp.log $(word $(1),$(POST_SYNTH)).vcd.log
 endef
 
-#FIXME: $(call simulate_post_synth,3)
 sim:
 	$(call simulate_post_synth,1)
 	$(call clean_post_synth_sim,1)

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_tdp/sim/bram18k_tdp_tb.v b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_tdp/sim/bram18k_tdp_tb.v
index ec5ca14..004f32c 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_tdp/sim/bram18k_tdp_tb.v
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram18k_tdp/sim/bram18k_tdp_tb.v

@@ -4,7 +4,7 @@
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
 //
-//     http://www.apache.org/licenses/LICENSE-2.0
+//		 http://www.apache.org/licenses/LICENSE-2.0
 //
 // Unless required by applicable law or agreed to in writing, software
 // distributed under the License is distributed on an "AS IS" BASIS,
@@ -24,29 +24,29 @@
 
 	reg clk_a;
 	reg rce_a_0;
-  reg rce_a_1;
+	reg rce_a_1;
 	reg [`ADDR_WIDTH0-1:0] ra_a_0;
-  reg [`ADDR_WIDTH1-1:0] ra_a_1;
+	reg [`ADDR_WIDTH1-1:0] ra_a_1;
 	wire [`DATA_WIDTH0-1:0] rq_a_0;
 	wire [`DATA_WIDTH1-1:0] rq_a_1;
 	reg wce_a_0;
-  reg wce_a_1;
+	reg wce_a_1;
 	reg [`ADDR_WIDTH0-1:0] wa_a_0;
-  reg [`ADDR_WIDTH1-1:0] wa_a_1;
+	reg [`ADDR_WIDTH1-1:0] wa_a_1;
 	reg [`DATA_WIDTH0-1:0] wd_a_0;
 	reg [`DATA_WIDTH1-1:0] wd_a_1;
 
 	reg clk_b;
 	reg rce_b_0;
-  reg rce_b_1;
+	reg rce_b_1;
 	reg [`ADDR_WIDTH0-1:0] ra_b_0;
-  reg [`ADDR_WIDTH1-1:0] ra_b_1;
+	reg [`ADDR_WIDTH1-1:0] ra_b_1;
 	wire [`DATA_WIDTH0-1:0] rq_b_0;
 	wire [`DATA_WIDTH1-1:0] rq_b_1;
 	reg wce_b_0;
-  reg wce_b_1;
+	reg wce_b_1;
 	reg [`ADDR_WIDTH0-1:0] wa_b_0;
-  reg [`ADDR_WIDTH1-1:0] wa_b_1;
+	reg [`ADDR_WIDTH1-1:0] wa_b_1;
 	reg [`DATA_WIDTH0-1:0] wd_b_0;
 	reg [`DATA_WIDTH1-1:0] wd_b_1;
 
@@ -54,22 +54,22 @@
 	initial clk_a = 0;
 	initial clk_b = 0;
 	initial ra_a_0 = 0;
-  initial ra_a_1 = 0;
+	initial ra_a_1 = 0;
 	initial ra_b_0 = 0;
-  initial ra_b_1 = 0;
+	initial ra_b_1 = 0;
 	initial rce_a_0 = 0;
-  initial rce_a_1 = 0;
+	initial rce_a_1 = 0;
 	initial rce_b_0 = 0;
-  initial rce_b_1 = 0;
+	initial rce_b_1 = 0;
 	initial wce_a_0 = 0;
-  initial wce_a_1 = 0;
+	initial wce_a_1 = 0;
 	initial wce_b_0 = 0;
-  initial wce_b_1 = 0;
+	initial wce_b_1 = 0;
 	initial forever #(PERIOD / 2.0) clk_a = ~clk_a;
 	initial begin
 		#(PERIOD / 4.0);
 		forever #(PERIOD / 2.0) clk_b = ~clk_b;
-	end  
+	end	 
 	initial begin
 		$dumpfile(`STRINGIFY(`VCD));
 		$dumpvars;
@@ -96,12 +96,12 @@
 	reg [`DATA_WIDTH1-1:0] expected_b_1;
 
 	always @(posedge clk_a) begin
-      expected_a_0 <= (a0 | (a0 << 20) | 20'h55000) & {`DATA_WIDTH0{1'b1}};
-      expected_a_1 <= ((a1+1) | ((a1+1) << 20) | 20'h55000) & {`DATA_WIDTH1{1'b1}};
+			expected_a_0 <= (a0 | (a0 << 20) | 20'h55000) & {`DATA_WIDTH0{1'b1}};
+			expected_a_1 <= ((a1+1) | ((a1+1) << 20) | 20'h55000) & {`DATA_WIDTH1{1'b1}};
 	end
 	always @(posedge clk_b) begin
-      expected_b_0 <= ((b0+2) | ((b0+2) << 20) | 20'h55000) & {`DATA_WIDTH0{1'b1}};
-      expected_b_1 <= ((b1+3) | ((b1+3) << 20) | 20'h55000) & {`DATA_WIDTH1{1'b1}};
+			expected_b_0 <= ((b0+2) | ((b0+2) << 20) | 20'h55000) & {`DATA_WIDTH0{1'b1}};
+			expected_b_1 <= ((b1+3) | ((b1+3) << 20) | 20'h55000) & {`DATA_WIDTH1{1'b1}};
 	end
 
 	wire error_a_0 = a0 != 0 ? (rq_a_0 !== expected_a_0) : 0;
@@ -158,10 +158,10 @@
 			end
 		end
 		done_a0 = 1'b1;
-    a0 = 0;
-	  // PORTs B0
-    @(posedge clk_b)
-    #2;
+		a0 = 0;
+		// PORTs B0
+		@(posedge clk_b)
+		#2;
 		// Write data
 		for (b0 = (1<<`ADDR_WIDTH0) / 2; b0 < (1<<`ADDR_WIDTH0); b0 = b0 + ADDR_INCR) begin
 			@(negedge clk_b) begin
@@ -189,10 +189,10 @@
 			end
 		end
 		done_b0 = 1'b1;
-	  b0 = (1<<`ADDR_WIDTH0) / 2;
-	  // PORTs A1
-    @(posedge clk_a)
-    #2;
+		b0 = (1<<`ADDR_WIDTH0) / 2;
+		// PORTs A1
+		@(posedge clk_a)
+		#2;
 		// Write data
 		for (a1 = 0; a1 < (1<<`ADDR_WIDTH1) / 2; a1 = a1 + ADDR_INCR) begin
 			@(negedge clk_a) begin
@@ -220,10 +220,10 @@
 			end
 		end
 		done_a1 = 1'b1;
-    a1 = 0;
-	  // PORTs B1
-    @(posedge clk_b)
-    #2;
+		a1 = 0;
+		// PORTs B1
+		@(posedge clk_b)
+		#2;
 		// Write data
 		for (b1 = (1<<`ADDR_WIDTH1) / 2; b1 < (1<<`ADDR_WIDTH1); b1 = b1 + ADDR_INCR) begin
 			@(negedge clk_b) begin
@@ -251,7 +251,7 @@
 			end
 		end
 		done_b1 = 1'b1;
-    b1 = (1<<`ADDR_WIDTH1) / 2;
+		b1 = (1<<`ADDR_WIDTH1) / 2;
 	end
 
 	// Scan for simulation finish
@@ -259,7 +259,7 @@
 		if (done_sim)
 			$finish_and_return( (error_a_0_cnt == 0 & error_b_0_cnt == 0 & error_a_1_cnt == 0 & error_b_1_cnt == 0) ? 0 : -1 );
 	end
-  
+	
 	case (`STRINGIFY(`TOP))
 		"dpram_18x1024_9x2048": begin
 			dpram_18x1024_9x2048 #() bram (

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_afifo/bram36k_afifo.v b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_afifo/bram36k_afifo.v
index 1b97e7f..2fc55ee 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_afifo/bram36k_afifo.v
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_afifo/bram36k_afifo.v

@@ -32,7 +32,7 @@
 output Overrun_Error, Underrun_Error;
 
 AFIFO_36K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
-        				 ) 
+                  )
   FIFO_INST    (
                 .DIN(DIN),
                 .PUSH(PUSH),
@@ -52,8 +52,7 @@
                 .Empty(Empty),
 
                 .DOUT(DOUT)
-         				);
-
+                );
 endmodule
 
 module af2048x18_2048x18 (DIN,PUSH,POP,clock0,clock1,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
@@ -74,7 +73,7 @@
 output Overrun_Error, Underrun_Error;
 
 AFIFO_36K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
-        				 ) 
+                  )
   FIFO_INST    (
                 .DIN(DIN),
                 .PUSH(PUSH),
@@ -94,8 +93,7 @@
                 .Empty(Empty),
 
                 .DOUT(DOUT)
-         				);
-
+                );
 endmodule
 
 module af4096x9_4096x9 (DIN,PUSH,POP,clock0,clock1,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
@@ -116,7 +114,7 @@
 output Overrun_Error, Underrun_Error;
 
 AFIFO_36K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
-        				 ) 
+                  )
   FIFO_INST    (
                 .DIN(DIN),
                 .PUSH(PUSH),
@@ -136,6 +134,5 @@
                 .Empty(Empty),
 
                 .DOUT(DOUT)
-         				);
-
+                );
 endmodule
\ No newline at end of file

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_afifo/sim/Makefile b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_afifo/sim/Makefile
index 8b777b5..7c93214 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_afifo/sim/Makefile
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_afifo/sim/Makefile

@@ -39,7 +39,6 @@
 	@rm -rf  $(word $(1),$(POST_SYNTH)).vcd $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).vvp.log $(word $(1),$(POST_SYNTH)).vcd.log
 endef
 
-# FIXME: $(call simulate_post_synth,5)
 sim:
 	$(call simulate_post_synth,1)
 	$(call clean_post_synth_sim,1)

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_afifo/sim/bram36k_afifo_tb.v b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_afifo/sim/bram36k_afifo_tb.v
index addf547..48424fc 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_afifo/sim/bram36k_afifo_tb.v
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_afifo/sim/bram36k_afifo_tb.v

@@ -4,7 +4,7 @@
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
 //
-//     http://www.apache.org/licenses/LICENSE-2.0
+//		 http://www.apache.org/licenses/LICENSE-2.0
 //
 // Unless required by applicable law or agreed to in writing, software
 // distributed under the License is distributed on an "AS IS" BASIS,
@@ -23,32 +23,32 @@
 	localparam ADDR_INCR = 1;
 
 	reg clk0;
-  reg clk1;
-  reg flush;
+	reg clk1;
+	reg flush;
 	reg pop;
 	wire [`DATA_WIDTH1-1:0] dout;
 	reg push;
 	reg [`DATA_WIDTH0-1:0] din;
-  wire almost_full,almost_empty;
-  wire full, empty;
-  wire full_watermark, empty_watermark;
-  wire overrun_error, underrun_error;
+	wire almost_full,almost_empty;
+	wire full, empty;
+	wire full_watermark, empty_watermark;
+	wire overrun_error, underrun_error;
 
-  initial 
-  begin
-    clk0 = 0;
-    clk1 = 0;
-    pop = 0;
-    push = 0;
-    flush = 1;
-    din = 0;
-    #40
-    flush = 0;
-  end
-  
+	initial 
+	begin
+		clk0 = 0;
+		clk1 = 0;
+		pop = 0;
+		push = 0;
+		flush = 1;
+		din = 0;
+		#40
+		flush = 0;
+	end
+	
 	initial forever #(PERIOD / 3.0) clk0 = ~clk0;
-  initial forever #(PERIOD / 2.0) clk1 = ~clk1;
-  
+	initial forever #(PERIOD / 2.0) clk1 = ~clk1;
+	
 	initial begin
 		$dumpfile(`STRINGIFY(`VCD));
 		$dumpvars;
@@ -58,12 +58,12 @@
 
 	reg done;
 	initial done = 1'b0;
-  
-  reg read_test;
+	
+	reg read_test;
 	initial read_test = 0;
 
 	reg [`DATA_WIDTH1-1:0] expected;
-  initial expected = 0;
+	initial expected = 0;
 
 	always @(posedge clk1) begin
 		expected <= (a | (a << 20) | 20'h55000) & {`DATA_WIDTH1{1'b1}};
@@ -80,7 +80,7 @@
 
 
 	initial #(50) begin
-    @(posedge clk0)
+		@(posedge clk0)
 		// Write data
 		for (a = 0; a < (1<<`ADDR_WIDTH0); a = a + ADDR_INCR) begin
 			@(negedge clk0) begin
@@ -118,59 +118,59 @@
 	case (`STRINGIFY(`TOP))
 		"af1024x36_1024x36": begin
 			af1024x36_1024x36 #() afifo (
-        .DIN(din),
-        .PUSH(push),
-        .POP(pop),
-        .clock0(clk0),
-        .clock1(clk1),
-        .Async_Flush(flush),
-        .Almost_Full(almost_full),
-        .Almost_Empty(almost_empty),
-        .Full(full),
-        .Empty(empty),
-        .Full_Watermark(full_watermark),
-        .Empty_Watermark(empty_watermark),
-        .Overrun_Error(overrun_error),
-        .Underrun_Error(underrun_error),
-        .DOUT(dout)
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk0),
+				.clock1(clk1),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
 			);
 		end
 		"af2048x18_2048x18": begin
 			af2048x18_2048x18 #() afifo (
-        .DIN(din),
-        .PUSH(push),
-        .POP(pop),
-        .clock0(clk0),
-        .clock1(clk1),
-        .Async_Flush(flush),
-        .Almost_Full(almost_full),
-        .Almost_Empty(almost_empty),
-        .Full(full),
-        .Empty(empty),
-        .Full_Watermark(full_watermark),
-        .Empty_Watermark(empty_watermark),
-        .Overrun_Error(overrun_error),
-        .Underrun_Error(underrun_error),
-        .DOUT(dout)
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk0),
+				.clock1(clk1),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
 			);
 		end
 		"af4096x9_4096x9": begin
 			af4096x9_4096x9 #() afifo (
-        .DIN(din),
-        .PUSH(push),
-        .POP(pop),
-        .clock0(clk0),
-        .clock1(clk1),
-        .Async_Flush(flush),
-        .Almost_Full(almost_full),
-        .Almost_Empty(almost_empty),
-        .Full(full),
-        .Empty(empty),
-        .Full_Watermark(full_watermark),
-        .Empty_Watermark(empty_watermark),
-        .Overrun_Error(overrun_error),
-        .Underrun_Error(underrun_error),
-        .DOUT(dout)
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk0),
+				.clock1(clk1),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
 			);
 		end		
 	endcase

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sdp/sim/Makefile b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sdp/sim/Makefile
index ca7d1af..05b231f 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sdp/sim/Makefile
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sdp/sim/Makefile

@@ -35,7 +35,6 @@
 	@rm -rf  $(word $(1),$(POST_SYNTH)).vcd $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).vvp.log $(word $(1),$(POST_SYNTH)).vcd.log
 endef
 
-# FIXME: $(call simulate_post_synth,5)
 sim:
 	$(call simulate_post_synth,1)
 	$(call clean_post_synth_sim,1)

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sdp/sim/bram36k_sdp_tb.v b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sdp/sim/bram36k_sdp_tb.v
index 1c003ec..c47b873 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sdp/sim/bram36k_sdp_tb.v
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sdp/sim/bram36k_sdp_tb.v

@@ -4,7 +4,7 @@
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
 //
-//     http://www.apache.org/licenses/LICENSE-2.0
+//		 http://www.apache.org/licenses/LICENSE-2.0
 //
 // Unless required by applicable law or agreed to in writing, software
 // distributed under the License is distributed on an "AS IS" BASIS,
@@ -103,7 +103,7 @@
 		"spram_36x1024": begin
 			spram_36x1024 #() bram (
 				.clock0(clk),
-        .clock1(clk),        
+				.clock1(clk),				 
 				.REN_i(rce),
 				.RD_ADDR_i(ra),
 				.RDATA_o(rq),
@@ -115,7 +115,7 @@
 		"spram_32x1024": begin
 			spram_32x1024 #() bram (
 				.clock0(clk),
-        .clock1(clk),        
+				.clock1(clk),				 
 				.REN_i(rce),
 				.RD_ADDR_i(ra),
 				.RDATA_o(rq),
@@ -127,7 +127,7 @@
 		"spram_18x2048": begin
 			spram_18x2048 #() bram (
 				.clock0(clk),
-        .clock1(clk),        
+				.clock1(clk),				 
 				.REN_i(rce),
 				.RD_ADDR_i(ra),
 				.RDATA_o(rq),
@@ -139,7 +139,7 @@
 		"spram_16x2048": begin
 			spram_16x2048 #() bram (
 				.clock0(clk),
-        .clock1(clk),        
+				.clock1(clk),				 
 				.REN_i(rce),
 				.RD_ADDR_i(ra),
 				.RDATA_o(rq),
@@ -151,7 +151,7 @@
 		"spram_9x4096": begin
 			spram_9x4096 #() bram (
 				.clock0(clk),
-        .clock1(clk),        
+				.clock1(clk),				 
 				.REN_i(rce),
 				.RD_ADDR_i(ra),
 				.RDATA_o(rq),
@@ -163,7 +163,7 @@
 		"spram_8x4096": begin
 			spram_8x4096 #() bram (
 				.clock0(clk),
-        .clock1(clk),        
+				.clock1(clk),				 
 				.REN_i(rce),
 				.RD_ADDR_i(ra),
 				.RDATA_o(rq),

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sfifo/bram36k_sfifo.v b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sfifo/bram36k_sfifo.v
index 63df3b2..d3bf2d6 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sfifo/bram36k_sfifo.v
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sfifo/bram36k_sfifo.v

@@ -32,7 +32,7 @@
 output Overrun_Error, Underrun_Error;
 
 SFIFO_36K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
-        				 ) 
+                  )
   FIFO_INST    (
                 .DIN(DIN),
                 .PUSH(PUSH),
@@ -51,8 +51,7 @@
                 .Empty(Empty),
 
                 .DOUT(DOUT)
-         				);
-
+                );
 endmodule
 
 module f2048x18_2048x18 (DIN,PUSH,POP,clock0,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
@@ -73,7 +72,7 @@
 output Overrun_Error, Underrun_Error;
 
 SFIFO_36K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
-        				 ) 
+                  )
   FIFO_INST    (
                 .DIN(DIN),
                 .PUSH(PUSH),
@@ -92,8 +91,7 @@
                 .Empty(Empty),
 
                 .DOUT(DOUT)
-         				);
-
+                );
 endmodule
 
 module f4096x9_4096x9 (DIN,PUSH,POP,clock0,Async_Flush,Almost_Full,Almost_Empty,Full,Empty,Full_Watermark,Empty_Watermark,Overrun_Error,Underrun_Error,DOUT);
@@ -114,7 +112,7 @@
 output Overrun_Error, Underrun_Error;
 
 SFIFO_36K_BLK  # (.WR_DATA_WIDTH(WR_DATA_WIDTH),.RD_DATA_WIDTH(RD_DATA_WIDTH),.UPAE_DBITS(UPAE_DBITS),.UPAF_DBITS(UPAF_DBITS)
-        				 ) 
+                  )
   FIFO_INST    (
                 .DIN(DIN),
                 .PUSH(PUSH),
@@ -133,6 +131,5 @@
                 .Empty(Empty),
 
                 .DOUT(DOUT)
-         				);
-
+                );
 endmodule
\ No newline at end of file

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sfifo/sim/Makefile b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sfifo/sim/Makefile
index 1cb26f3..e31e1d0 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sfifo/sim/Makefile
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sfifo/sim/Makefile

@@ -39,7 +39,6 @@
 	@rm -rf  $(word $(1),$(POST_SYNTH)).vcd $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).vvp.log $(word $(1),$(POST_SYNTH)).vcd.log
 endef
 
-# FIXME: $(call simulate_post_synth,5)
 sim:
 	$(call simulate_post_synth,1)
 	$(call clean_post_synth_sim,1)

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sfifo/sim/bram36k_sfifo_tb.v b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sfifo/sim/bram36k_sfifo_tb.v
index df2362c..76be519 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sfifo/sim/bram36k_sfifo_tb.v
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_sfifo/sim/bram36k_sfifo_tb.v

@@ -4,7 +4,7 @@
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
 //
-//     http://www.apache.org/licenses/LICENSE-2.0
+//		 http://www.apache.org/licenses/LICENSE-2.0
 //
 // Unless required by applicable law or agreed to in writing, software
 // distributed under the License is distributed on an "AS IS" BASIS,
@@ -23,29 +23,29 @@
 	localparam ADDR_INCR = 1;
 
 	reg clk;
-  reg flush;
+	reg flush;
 	reg pop;
 	wire [`DATA_WIDTH1-1:0] dout;
 	reg push;
 	reg [`DATA_WIDTH0-1:0] din;
-  wire almost_full,almost_empty;
-  wire full, empty;
-  wire full_watermark, empty_watermark;
-  wire overrun_error, underrun_error;
+	wire almost_full,almost_empty;
+	wire full, empty;
+	wire full_watermark, empty_watermark;
+	wire overrun_error, underrun_error;
 
-  initial 
-  begin
-    clk = 0;
-    pop = 0;
-    push = 0;
-    flush = 1;
-    din = 0;
-    #40
-    flush = 0;
-  end
-  
+	initial 
+	begin
+		clk = 0;
+		pop = 0;
+		push = 0;
+		flush = 1;
+		din = 0;
+		#40
+		flush = 0;
+	end
+	
 	initial forever #(PERIOD / 3.0) clk = ~clk;
-  
+	
 	initial begin
 		$dumpfile(`STRINGIFY(`VCD));
 		$dumpvars;
@@ -55,12 +55,12 @@
 
 	reg done;
 	initial done = 1'b0;
-  
+	
 	reg read_test;
 	initial read_test = 0;
 
 	reg [`DATA_WIDTH1-1:0] expected;
-  initial expected = 0;
+	initial expected = 0;
 
 	always @(posedge clk) begin
 		expected <= (a | (a << 20) | 20'h55000) & {`DATA_WIDTH1{1'b1}};
@@ -76,7 +76,7 @@
 	end
 
 	initial #(50) begin
-    @(posedge clk)
+		@(posedge clk)
 		// Write data
 		for (a = 0; a < (1<<`ADDR_WIDTH0); a = a + ADDR_INCR) begin
 			@(negedge clk) begin
@@ -114,56 +114,56 @@
 	case (`STRINGIFY(`TOP))
 		"f1024x36_1024x36": begin
 			f1024x36_1024x36 #() afifo (
-        .DIN(din),
-        .PUSH(push),
-        .POP(pop),
-        .clock0(clk),
-        .Async_Flush(flush),
-        .Almost_Full(almost_full),
-        .Almost_Empty(almost_empty),
-        .Full(full),
-        .Empty(empty),
-        .Full_Watermark(full_watermark),
-        .Empty_Watermark(empty_watermark),
-        .Overrun_Error(overrun_error),
-        .Underrun_Error(underrun_error),
-        .DOUT(dout)
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
 			);
 		end
 		"f2048x18_2048x18": begin
 			f2048x18_2048x18 #() afifo (
-        .DIN(din),
-        .PUSH(push),
-        .POP(pop),
-        .clock0(clk),
-        .Async_Flush(flush),
-        .Almost_Full(almost_full),
-        .Almost_Empty(almost_empty),
-        .Full(full),
-        .Empty(empty),
-        .Full_Watermark(full_watermark),
-        .Empty_Watermark(empty_watermark),
-        .Overrun_Error(overrun_error),
-        .Underrun_Error(underrun_error),
-        .DOUT(dout)
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
 			);
 		end
 		"f4096x9_4096x9": begin
 			f4096x9_4096x9 #() afifo (
-        .DIN(din),
-        .PUSH(push),
-        .POP(pop),
-        .clock0(clk),
-        .Async_Flush(flush),
-        .Almost_Full(almost_full),
-        .Almost_Empty(almost_empty),
-        .Full(full),
-        .Empty(empty),
-        .Full_Watermark(full_watermark),
-        .Empty_Watermark(empty_watermark),
-        .Overrun_Error(overrun_error),
-        .Underrun_Error(underrun_error),
-        .DOUT(dout)
+				.DIN(din),
+				.PUSH(push),
+				.POP(pop),
+				.clock0(clk),
+				.Async_Flush(flush),
+				.Almost_Full(almost_full),
+				.Almost_Empty(almost_empty),
+				.Full(full),
+				.Empty(empty),
+				.Full_Watermark(full_watermark),
+				.Empty_Watermark(empty_watermark),
+				.Overrun_Error(overrun_error),
+				.Underrun_Error(underrun_error),
+				.DOUT(dout)
 			);
 		end		
 	endcase

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_tdp/sim/Makefile b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_tdp/sim/Makefile
index 2a0c20d..6ce8344 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_tdp/sim/Makefile
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_tdp/sim/Makefile

@@ -35,7 +35,6 @@
 	@rm -rf  $(word $(1),$(POST_SYNTH)).vcd $(word $(1),$(POST_SYNTH)).vvp $(word $(1),$(POST_SYNTH)).vvp.log $(word $(1),$(POST_SYNTH)).vcd.log
 endef
 
-# FIXME: $(call simulate_post_synth,5)
 sim:
 	$(call simulate_post_synth,1)
 	$(call clean_post_synth_sim,1)

diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_tdp/sim/bram36k_tdp_tb.v b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_tdp/sim/bram36k_tdp_tb.v
index 01de7e7..646561a 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_tdp/sim/bram36k_tdp_tb.v
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/bram36k_tdp/sim/bram36k_tdp_tb.v

@@ -4,7 +4,7 @@
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
 //
-//     http://www.apache.org/licenses/LICENSE-2.0
+//		 http://www.apache.org/licenses/LICENSE-2.0
 //
 // Unless required by applicable law or agreed to in writing, software
 // distributed under the License is distributed on an "AS IS" BASIS,
@@ -157,7 +157,7 @@
 		if (done_sim)
 			$finish_and_return( (error_a_cnt == 0 & error_b_cnt == 0) ? 0 : -1 );
 	end
-  
+	
 	case (`STRINGIFY(`TOP))
 		"dpram_36x1024": begin
 			dpram_36x1024 #() bram (
@@ -168,7 +168,7 @@
 				.WEN1_i(wce_a),
 				.WR1_ADDR_i(wa_a),
 				.WDATA1_i(wd_a),
-        
+				
 				.clock1(clk_b),
 				.REN2_i(rce_b),
 				.RD2_ADDR_i(ra_b),
@@ -187,7 +187,7 @@
 				.WEN1_i(wce_a),
 				.WR1_ADDR_i(wa_a),
 				.WDATA1_i(wd_a),
-        
+				
 				.clock1(clk_b),
 				.REN2_i(rce_b),
 				.RD2_ADDR_i(ra_b),
@@ -206,7 +206,7 @@
 				.WEN1_i(wce_a),
 				.WR1_ADDR_i(wa_a),
 				.WDATA1_i(wd_a),
-        
+				
 				.clock1(clk_b),
 				.REN2_i(rce_b),
 				.RD2_ADDR_i(ra_b),