XDC plugin: Use common plugin test Makefile Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>

diff --git a/xdc-plugin/tests/Makefile b/xdc-plugin/tests/Makefile
index 714ed73..76d2241 100644
--- a/xdc-plugin/tests/Makefile
+++ b/xdc-plugin/tests/Makefile

@@ -3,51 +3,23 @@
 # io_loc_pairs - test for LOC property being set on IOBUFs as the IO_LOC_PAIRS parameter
 # minilitex_ddr_arty - litex design with more types of IOBUFS including differential
 # package_pins - test for PACKAGE_PIN property being set on IOBUFs as the IO_LOC_PAIRS parameter
-
 TESTS = counter \
 	port_indexes \
 	io_loc_pairs \
 	minilitex_ddr_arty \
 	package_pins
 
-counter_verify = $(call compare_json,counter)
-port_indexes_verify = $(call compare_json,port_indexes) && test $$(grep "'unknown' proc command handler" port_indexes/port_indexes.txt | wc -l) -eq 2
-io_loc_pairs_verify = $(call compare_json,io_loc_pairs)
-minilitex_ddr_arty_verify = $(call compare_json,minilitex_ddr_arty)
-package_pins_verify = $(call compare_json,package_pins)
+include $(shell pwd)/../../Makefile_test.common
 
-all: $(TESTS)
+json_test = python compare_output_json.py --json $(1)/$(1).json --golden $(1)/$(1).golden.json
 
-compare_json = python compare_output_json.py --json $(1)/$(1).json --golden $(1)/$(1)_golden.json
-
-define test_tpl =
-$(1): $(1)/$(1).json
-	$$($(1)_verify)
-	RETVAL=$$$$? ; \
-	if [ $$$$RETVAL -eq 0 ]; then \
-		echo "$(1) PASS"; \
-		true; \
-	else \
-		echo "$(1) FAIL"; \
-		false; \
-	fi
-
-$(1)/$(1).json: $(1)/$(1).v
-	cd $(1); \
-	PART_JSON=../xc7a35tcsg324-1.json \
-	OUT_JSON=$(1).json \
-	INPUT_XDC_FILE=$(1).xdc \
-	yosys -p "tcl $(1).tcl" $(1).v -l yosys.log
-
-update_$(1): $(1)/$(1).json
-	@python compare_output_json.py --json $$< --golden $(1)/$(1)_golden.json --update
-
+define json_update =
+$(1)_update_json:
+	python compare_output_json.py --json $(1)/$(1).json --golden $(1)/$(1).golden.json --update
 endef
 
-$(foreach test,$(TESTS),$(eval $(call test_tpl,$(test))))
-
-update: $(foreach test,$(TESTS),update_$(test))
-
-
-clean:
-	rm -rf $(foreach test,$(TESTS),$(test)/$(test).json $(test)/$(test).eblif $(test)/$(test).txt $(test)/yosys.log)
+counter_verify = $(call json_test,counter)
+port_indexes_verify = $(call json_test,port_indexes) && test $$(grep "'unknown' proc command handler" port_indexes/port_indexes.txt | wc -l) -eq 2
+io_loc_pairs_verify = $(call json_test,io_loc_pairs)
+minilitex_ddr_arty_verify = $(call json_test,minilitex_ddr_arty)
+package_pins_verify = $(call json_test,package_pins)

diff --git a/xdc-plugin/tests/counter/counter_golden.json b/xdc-plugin/tests/counter/counter.golden.json
similarity index 100%
rename from xdc-plugin/tests/counter/counter_golden.json
rename to xdc-plugin/tests/counter/counter.golden.json


diff --git a/xdc-plugin/tests/counter/counter.tcl b/xdc-plugin/tests/counter/counter.tcl
index 696dc4d..b7090c8 100644
--- a/xdc-plugin/tests/counter/counter.tcl
+++ b/xdc-plugin/tests/counter/counter.tcl

@@ -2,12 +2,15 @@
 plugin -i xdc
 #Import the commands from the plugins to the tcl interpreter
 yosys -import
+
+read_verilog $::env(DESIGN_TOP).v
+
 # -flatten is used to ensure that the output eblif has only one module.
 # Some of symbiflow expects eblifs with only one module.
 synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp
 
 #Read the design constraints
-read_xdc -part_json $::env(PART_JSON) $::env(INPUT_XDC_FILE)
+read_xdc -part_json ../xc7a35tcsg324-1.json $::env(DESIGN_TOP).xdc
 
 # Write the design in JSON format.
-write_json $::env(OUT_JSON)
+write_json $::env(DESIGN_TOP).json

diff --git a/xdc-plugin/tests/io_loc_pairs/io_loc_pairs_golden.json b/xdc-plugin/tests/io_loc_pairs/io_loc_pairs.golden.json
similarity index 100%
rename from xdc-plugin/tests/io_loc_pairs/io_loc_pairs_golden.json
rename to xdc-plugin/tests/io_loc_pairs/io_loc_pairs.golden.json


diff --git a/xdc-plugin/tests/io_loc_pairs/io_loc_pairs.tcl b/xdc-plugin/tests/io_loc_pairs/io_loc_pairs.tcl
index 8c0a57c..b7090c8 100644
--- a/xdc-plugin/tests/io_loc_pairs/io_loc_pairs.tcl
+++ b/xdc-plugin/tests/io_loc_pairs/io_loc_pairs.tcl

@@ -3,12 +3,14 @@
 #Import the commands from the plugins to the tcl interpreter
 yosys -import
 
+read_verilog $::env(DESIGN_TOP).v
+
 # -flatten is used to ensure that the output eblif has only one module.
 # Some of symbiflow expects eblifs with only one module.
 synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp
 
 #Read the design constraints
-read_xdc -part_json $::env(PART_JSON) $::env(INPUT_XDC_FILE)
+read_xdc -part_json ../xc7a35tcsg324-1.json $::env(DESIGN_TOP).xdc
 
 # Write the design in JSON format.
-write_json $::env(OUT_JSON)
+write_json $::env(DESIGN_TOP).json

diff --git a/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty_golden.json b/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.golden.json
similarity index 100%
rename from xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty_golden.json
rename to xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.golden.json


diff --git a/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.tcl b/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.tcl
index 9597cd4..af91ce6 100644
--- a/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.tcl
+++ b/xdc-plugin/tests/minilitex_ddr_arty/minilitex_ddr_arty.tcl

@@ -2,14 +2,15 @@
 plugin -i xdc
 #Import the commands from the plugins to the tcl interpreter
 yosys -import
+
+read_verilog $::env(DESIGN_TOP).v
 read_verilog VexRiscv_Lite.v
 # -flatten is used to ensure that the output eblif has only one module.
 # Some of symbiflow expects eblifs with only one module.
 synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp
 
 #Read the design constraints
-read_xdc -part_json $::env(PART_JSON) $::env(INPUT_XDC_FILE)
+read_xdc -part_json ../xc7a35tcsg324-1.json $::env(DESIGN_TOP).xdc
 
 # Write the design in JSON format.
-write_json $::env(OUT_JSON)
-write_blif -attr -param -cname -conn counter.eblif
+write_json $::env(DESIGN_TOP).json

diff --git a/xdc-plugin/tests/package_pins/package_pins_golden.json b/xdc-plugin/tests/package_pins/package_pins.golden.json
similarity index 100%
rename from xdc-plugin/tests/package_pins/package_pins_golden.json
rename to xdc-plugin/tests/package_pins/package_pins.golden.json


diff --git a/xdc-plugin/tests/package_pins/package_pins.tcl b/xdc-plugin/tests/package_pins/package_pins.tcl
index 8c0a57c..66bd21d 100644
--- a/xdc-plugin/tests/package_pins/package_pins.tcl
+++ b/xdc-plugin/tests/package_pins/package_pins.tcl

@@ -3,12 +3,13 @@
 #Import the commands from the plugins to the tcl interpreter
 yosys -import
 
+read_verilog $::env(DESIGN_TOP).v
 # -flatten is used to ensure that the output eblif has only one module.
 # Some of symbiflow expects eblifs with only one module.
 synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp
 
 #Read the design constraints
-read_xdc -part_json $::env(PART_JSON) $::env(INPUT_XDC_FILE)
+read_xdc -part_json ../xc7a35tcsg324-1.json $::env(DESIGN_TOP).xdc
 
 # Write the design in JSON format.
-write_json $::env(OUT_JSON)
+write_json $::env(DESIGN_TOP).json

diff --git a/xdc-plugin/tests/port_indexes/port_indexes_golden.json b/xdc-plugin/tests/port_indexes/port_indexes.golden.json
similarity index 100%
rename from xdc-plugin/tests/port_indexes/port_indexes_golden.json
rename to xdc-plugin/tests/port_indexes/port_indexes.golden.json


diff --git a/xdc-plugin/tests/port_indexes/port_indexes.tcl b/xdc-plugin/tests/port_indexes/port_indexes.tcl
index ac05de3..ed35c69 100644
--- a/xdc-plugin/tests/port_indexes/port_indexes.tcl
+++ b/xdc-plugin/tests/port_indexes/port_indexes.tcl

@@ -3,6 +3,8 @@
 #Import the commands from the plugins to the tcl interpreter
 yosys -import
 
+read_verilog $::env(DESIGN_TOP).v
+
 # -flatten is used to ensure that the output eblif has only one module.
 # Some of symbiflow expects eblifs with only one module.
 synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp
@@ -19,7 +21,7 @@
 	puts $fp $result
 }
 #Read the design constraints
-read_xdc -part_json $::env(PART_JSON) $::env(INPUT_XDC_FILE)
+read_xdc -part_json ../xc7a35tcsg324-1.json $::env(DESIGN_TOP).xdc
 
 if {[catch {invalid command} result]} {
 	close $fp
@@ -30,4 +32,4 @@
 close $fp
 
 # Write the design in JSON format.
-write_json $::env(OUT_JSON)
+write_json $::env(DESIGN_TOP).json